Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package includes a package substrate, at least one dam structure extending on the package substrate to surround substrate pads and defining an inner space that accommodates the substrate pads on the package substrate, a first semiconductor on the package substrate, a second semiconductor chip attached to the first semiconductor chip by an adhesive film, bonding wires electrically connecting chip pads of the second semiconductor chip to the substrate pads of the package substrate, a first underfill member filling a gap between the package substrate and the first semiconductor chip, a second underfill member filling the inner space of the at least one dam structure, and a molding member covering the first semiconductor chip, the second semiconductor chip and the first and second underfill members on the package substrate.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a package substrate having an upper surface and a lower surface opposite the upper surface, the package substrate including a first region and a second region surrounding the first region, the package substrate including first substrate pads on the upper surface in the first region and second substrate pads on the upper surface in the second region;   at least one dam structure protruding from the upper surface of the package substrate and having a first height from the upper surface of the package substrate, the at least one dam structure extending to surround the second substrate pads and defining an inner space that accommodates the second substrate pads on the package substrate;   a first semiconductor chip in the first region on the package substrate, the first semiconductor chip having a first surface with first chip pads thereon, the first surface facing the package substrate;   a second semiconductor chip attached to a second surface of the first semiconductor chip opposite to the first surface by an adhesive film, the second semiconductor chip having a third surface and a fourth surface opposite to a third surface, the fourth surface having second chip pads thereon, and the third surface facing the first semiconductor chip;   bonding wires electrically connecting the second chip pads of the second semiconductor chip to the second substrate pads of the package substrate;   a first underfill member filling a gap between the first semiconductor chip and the upper surface of the package substrate;   a second underfill member at least partially filling the inner space of the at least one dam structure; and   a molding member covering the first semiconductor chip, the second semiconductor chip, and the first and second underfill members on the package substrate.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the second substrate pads include a first group of pads along a first side portion of the package substrate that extends in a direction perpendicular to the upper surface of the package substrate and parallel to a first direction, and a second group of pads along a second side portion of the package substrate that is adjacent to the first side portion and extends in a direction parallel to a second direction perpendicular to the first direction, and
 The at least one dam structure includes a first dam structure surrounding the first group of pads and a second dam structure surrounding the second group of pads.   
     
     
         3 . The semiconductor package of  claim 1 , wherein the first height of the at least one dam structure is within a range of 10 μm to 30 μm. 
     
     
         4 . The semiconductor package of  claim 1 , wherein a width of the at least one dam structure is within a range of 100 μm to 200 μm. 
     
     
         5 . The semiconductor package of  claim 1 , wherein a distance between an inner wall of the at least one dam structure and the second substrate pads is within a range of 100 μm to 250 μm. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the second underfill member covers one end portion of a bonding wire from among the bonding wires that is bonded to a second substrate pad from among the second substrate pads. 
     
     
         7 . The semiconductor package of  claim 1 , wherein the first underfill member and the second underfill member include a same material. 
     
     
         8 . The semiconductor package of  claim 7 , wherein the first and second underfill members include an epoxy material. 
     
     
         9 . The semiconductor package of  claim 1 , wherein the adhesive film includes a die attach film. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the first semiconductor chip is mounted on the first substrate pads via conductive bumps that are on the first chip pads. 
     
     
         11 . A semiconductor package, comprising:
 a package substrate including a first region and a second region surrounding the first region, the package substrate having first substrate pads in the first region and second substrate pads in the second region along at least one side portion of the package substrate;   at least one dam structure extending to surround the second substrate pads on an upper surface of the package substrate and defining an inner space that accommodates the second substrate pads on the upper surface of the package substrate;   a first semiconductor chip in the first region of the package substrate and mounted on the first substrate pads via conductive bumps that are on first chip pads of the first semiconductor chip;   a second semiconductor chip on the first semiconductor chip, the second semiconductor chip having a backside surface and a front surface opposite the backside surface, the front surface having second chip pads thereon, and the backside surface faces the first semiconductor chip;   bonding wires electrically connecting the second chip pads of the second semiconductor chip to the second substrate pads of the package substrate;   a first underfill member filling a gap between the first semiconductor chip and the package substrate;   a second underfill member filling the inner space of the at least one dam structure, the second underfill member provided on the second substrate pads; and   a molding member covering the first semiconductor chip, the second semiconductor chip, and the first and second underfill members on the package substrate.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the first chip pads are on a first surface of the first semiconductor chip, and the first surface faces the package substrate. 
     
     
         13 . The semiconductor package of  claim 11 , wherein the second semiconductor chip is attached to an upper surface of the first semiconductor chip by an adhesive film and exposes a portion of the upper surface of the first semiconductor chip. 
     
     
         14 . The semiconductor package of  claim 13 , wherein the adhesive film includes a die attach film. 
     
     
         15 . The semiconductor package of  claim 11 , wherein a height of the at least one dam structure from the package substrate is within a range of 10 μm to 30 μm. 
     
     
         16 . The semiconductor package of  claim 11 , wherein a width of the at least one dam structure is within a range of 100 μm to 200 μm. 
     
     
         17 . The semiconductor package of  claim 11 , wherein a gap between an inner wall of the at least one dam structure and the second substrate pads is within a range of 100 μm to 250 μm. 
     
     
         18 . The semiconductor package of  claim 11 , wherein the second underfill member covers one end portion of a bonding wire from among the bonding wires that is bonded to a second substrate pad from among the second substrate pads. 
     
     
         19 . The semiconductor package of  claim 11 , wherein the first underfill member and the second underfill member include a same material. 
     
     
         20 . A semiconductor package, comprising:
 a package substrate including a first region and a second region surrounding the first region, the package substrate having first substrate pads in the first region and second substrate pads in the second region along at least one side portion of the package substrate;   at least one dam structure protruding from an upper surface of the package substrate to having a first height from the package substrate, the at least one dam structure extending to surround the second substrate pads and defining an inner space that accommodates the second substrate pads on the package substrate;   a first semiconductor chip in the first region of the package substrate, the first semiconductor chip having a first surface with first chip pads thereon, the first surface facing the package substrate, the first semiconductor chip mounted on the first substrate pads via conductive bumps on the first chip pads;   a second semiconductor chip on a second surface of the first semiconductor chip opposite to the first surface by an adhesive film, the second semiconductor chip exposing a portion of the second surface of the first semiconductor chip, the second semiconductor chip having a fourth surface opposite to a third surface, the fourth surface having second chip pads thereon, and the third surface facing the first semiconductor chip;   bonding wires electrically connecting the second chip pads of the second semiconductor chip to the second substrate pads of the package substrate;   a first underfill member filling a gap between the first semiconductor chip and the package substrate;   a second underfill member filling the inner space of the at least one dam structure and on the second substrate pads; and   a molding member covering the first semiconductor chip, the second semiconductor chip, and the first and second underfill members on the package substrate,   wherein the first height of the at least one dam structure is within a range of 10 μm to 30 μm.