Semiconductor storage device

Abstract

[Problem] To perform more appropriate reading operation. [Solution] A semiconductor storage device includes: one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage; and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes: a first storage element having a resistance value corresponding to a first status or a second status; and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes: a second storage element having a resistance value corresponding to a first status or a second status; and a second cell transistor connected between the second storage element and the third voltage supply line.

1 . A semiconductor storage device, comprising:
 one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage; and   one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage,   wherein   each of the first memory cells includes:   a first storage element having a resistance value corresponding to a first status or a second status; and   a first cell transistor connected between the first storage element and the first voltage supply line,   each of the second memory cells includes:   a second storage element having a resistance value corresponding to a first status or a second status; and   a second cell transistor connected between the second storage element and the third voltage supply line, and   the semiconductor storage device further includes:   a reference voltage generation unit that generates a reference voltage having a voltage level between a voltage that is generated by having the first storage elements and the second storage elements biased based on the first voltage and the second voltage, the first storage elements and the second storage elements having a resistance value corresponding to the first status, and a voltage that is generated by having the first storage elements and the second storage elements biased based on the first voltage and the second voltage, the first storage elements and the second storage element having a resistance value corresponding to the second status; and   a comparison unit that compares the reference voltage with a voltage that is generated by having the first storage elements or the second storage elements biased based on the first voltage and the second voltage,   the reference voltage generation unit including:   a first reference voltage generation unit that is connected between the first voltage supply line and the second voltage supply line and generates the reference voltage when a reading operation of the second memory cells is performed; and   a second reference voltage generation unit that is connected between the second voltage supply line and the third voltage supply line and generates the reference voltage when a reading operation of the first memory cells is performed, and   the first reference voltage generation unit and the second reference voltage generation unit being arranged approximately symmetrically with the second voltage supply line therebetween.   
     
     
         2 . The semiconductor storage device according to  claim 1 , wherein the number of first memory cells and the number of second memory cells are the same. 
     
     
         3 . The semiconductor storage device according to  claim 1 , wherein the first memory cells and the second memory cells are arranged approximately symmetrically with the second voltage supply line therebetween. 
     
     
         4 . The semiconductor storage device according to  claim 1 , further comprising:
 a voltage supply unit that, in a reading operation of the first memory cells or the second memory cells, causes the first voltage supply line and the third voltage supply line to supply the first voltage, causes the second voltage supply line to supply the second voltage, and stops the supply of the first voltage; and   a cell transistor control unit that turns on the first cell transistors of the first cells to be read or the second cell transistors of the second memory cells to be read while the supply of the first voltage is being stopped.   
     
     
         5 . The semiconductor storage device according to  claim 4 , wherein a potential difference between the first voltage and the second voltage is a potential difference corresponding to a difference in voltage change rate between the first voltage supply line and the third voltage supply line that is obtained after the cell transistor control unit turns on the first cell transistors or the second cell transistors. 
     
     
         6 . The semiconductor storage device according to  claim 4 , wherein the second voltage supply line is fixed to the second voltage. 
     
     
         7 . (canceled) 
     
     
         8 . (canceled) 
     
     
         9 . (canceled) 
     
     
         10 . The semiconductor storage device according to  claim 1 , wherein the first reference voltage generation unit is configured to include:
 a first reference resistance element; and   a first reference transistor that is connected between the first reference resistance element and the first voltage supply line, and   the second reference voltage generation unit is configured to include:   a second reference resistance element; and   a second reference transistor that is connected between the second reference resistance element and the third voltage supply line.   
     
     
         11 . The semiconductor storage device according to  claim 1 , wherein the comparison unit is configured to compare the reference voltage with the voltage that is generated by having the first storage elements or the second storage elements biased based on the first voltage and the second voltage, by comparing a voltage of the first voltage supply line with a voltage of the third voltage supply line, and
 the semiconductor storage device further includes a comparison control unit that causes the comparison unit to start comparing at a timing corresponding to the voltages of the first voltage supply line and the third voltage supply line.   
     
     
         12 . The semiconductor storage device according to  claim 11 , wherein the comparison control unit is configured to,
 when the first voltage is higher than the second voltage, cause the comparison unit to start comparing at a timing at which the voltage of at least either one of the first voltage supply line and the third voltage supply line becomes lower than a first predetermined value, and   when the first voltage is lower than the second voltage, cause the comparison unit to start comparing at a timing at which the voltage of at least either one of the first voltage supply line and the third voltage supply line becomes higher than a second predetermined value.   
     
     
         13 . The semiconductor storage device according to  claim 1 , wherein, in a reading operation, the first voltage is higher than the second voltage. 
     
     
         14 . The semiconductor storage device according to  claim 13 , wherein, in a writing operation, the first voltage is lower than the second voltage, and
 the second voltage obtained in a writing operation is higher than the first voltage obtained in a reading operation.   
     
     
         15 . The semiconductor storage device according to  claim 13 , wherein, in a writing operation, the first voltage is higher than the second voltage, and
 the first voltage obtained in a writing operation is higher than the first voltage obtained in a reading operation.   
     
     
         16 . The semiconductor storage device according to  claim 1 , wherein, in a reading operation, the first voltage is lower than the second voltage. 
     
     
         17 . The semiconductor storage device according to  claim 16 , wherein, in a writing operation, the first voltage is lower than the second voltage, and
 the second voltage obtained in a writing operation is higher than the second voltage obtained in a reading operation.