Array substrate, display panel and display apparatus

Abstract

An array substrate includes a substrate, first power supply signal lines, data lines and fan-out lines. The fan-out lines each include a first sub-line and a second sub-line; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line, and the second sub-line is insulated from remaining data lines of the data lines. The first sub-line and main structures of the data lines are disposed in a same layer. An orthographic projection, on the substrate, of a first sub-line passing through a column of sub-pixel regions is substantially located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of sub-pixel regions and an orthographic projection, on the substrate, of a data line passing through the column of sub-pixel regions.

1 . An array substrate, comprising:
 a substrate having a display area and a peripheral area;   a plurality of first power supply signal lines located on a first side of the substrate and located in the display area; wherein the plurality of first power supply signal lines each extend in a first direction and are sequentially arranged in a second direction; the second direction intersects the first direction, and the second direction and the first direction are both parallel to the substrate;   a plurality of data lines located on the first side of the substrate and located in the display area; wherein the plurality of data lines each extend in the first direction and are sequentially arranged in the second direction; a data line is adjacent to a first power supply signal line; and   a plurality of fan-out lines located on the first side of the substrate; wherein the plurality of fan-out lines each include a first sub-line and a second sub-line; the first sub-line extends in the first direction and extends from the peripheral area to the display area; the second sub-line extends in the second direction and is located in the display area; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line of the plurality of data lines, and the second sub-line is insulated from remaining data lines of the plurality of data lines; wherein   main structures of the plurality of data lines are located on a side of the first power supply signal lines away from the substrate, and the first sub-line and the main structures of the plurality of data lines are disposed in a same layer;   the display area has sub-pixel regions in a plurality of rows and a plurality of columns; an orthographic projection, on the substrate, of a first sub-line passing through a column of sub-pixel regions is substantially located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of sub-pixel regions and an orthographic projection, on the substrate, of a data line passing through the column of sub-pixel regions.   
     
     
         2 . The array substrate according to  claim 1 , wherein
 the peripheral area includes a lead-out region located on a side of the display area; the first sub-line extends from the lead-out region to the display area, and a length of at least one first sub-line is not greater than half a dimension of the display area in the first direction; or   the peripheral area includes the lead-out region located on the side of the display area; the first sub-line extends from the lead-out region to the display area, and the length of the at least one first sub-line is not greater than half the dimension of the display area in the first direction; a direction from a center line, in the second direction, of the display area to any side of the display area in the second direction is a first setting direction; lengths of portions, located in the display area, of first sub-lines of all first sub-lines included in the plurality of fan-out lines sequentially decrease in the first setting direction.   
     
     
         3 . (canceled) 
     
     
         4 . The array substrate according to  claim 1 , wherein
 the main structures of the plurality of data lines each include a plurality of main lines;   at least part of the plurality of data lines each further include at least one jumper wire, and the at least one jumper wire and the first power supply signal lines are disposed in another same layer; in a same data line, at least one jumper wire and main lines are alternately electrically connected to one other through via holes;   the second sub-line and the plurality of main lines are arranged in the same layer, and each of at least one second sub-line crosses a jumper wire of at least one data line.   
     
     
         5 . The array substrate according to  claim 4 , further comprising:
 an active film layer disposed between the at least one jumper wire and the substrate; wherein   a jumper wire has an extension portion, and an end of the extension portion is connected to the active film layer through a via hole.   
     
     
         6 . The array substrate according to  claim 4 , wherein
 a minimum closed graphic region where all second sub-lines, located on a same side of a center line of the display area in the second direction, are located is a first wiring region; at least a portion, located within the first wiring region, of each of data lines passing through the first wiring region is provided with a jumper wire.   
     
     
         7 . The array substrate according to  claim 4 , wherein
 a direction from a center line, in the second direction, of the display area to any side of the display area in the second direction is a first setting direction;   numbers of jumper wires respectively included in data lines firstly increase and then decrease in the first setting direction.   
     
     
         8 . The array substrate according to  claim 6 , wherein
 of all the data lines passing through the first wiring region, a data line of which a portion located within the first wiring region has a greatest number of jumper wires is a first-type data line, and data lines other than the first-type data line are second-type data lines; a portion, located outside the first wiring region, of each of all the second-type data lines is provided with a jumper wire; a number of jumper wires included in each of all the second-type data lines is equal to a number of jumper wires included in the first-type data line; or   of all the data lines passing through the first wiring region, the data line of which the portion located within the first wiring region has the greatest number of jumper wires is the first-type data line, and the data lines other than the first-type data line are the second-type data lines; the portion, located outside the first wiring region, of each of all the second-type data lines is provided with the jumper wire; the number of jumper wires included in each of all the second-type data lines is equal to the number of jumper wires included in the first-type data line; an end of the first sub-line connected to the second sub-line is a first end, and another end of the first sub-line is a second end; a direction from the second end to the first end is a second setting direction; of each of all the second-type data lines, the jumper wire located within the first wiring region and the jumper wire located outside the first wiring region are arranged in the second setting direction.   
     
     
         9 . (canceled) 
     
     
         10 . The array substrate according to  claim 6 , wherein
 a portion, located outside the first wiring region, of each of all the data lines passing through the first wiring region is provided with a jumper wire; a number of jumper wires included in each data line is equal; jumper wires included in all the data lines passing through the first wiring region are arranged in rows in the first direction.   
     
     
         11 . The array substrate according to  claim 4 , comprising:
 a first source-drain metal layer located on the first side of the substrate; and   a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate;   wherein the first power supply signal lines and the at least one jumper wire are located in the first source-drain metal layer, and the first sub-line, the second sub-line and the plurality of main lines are located in the second source-drain metal layer.   
     
     
         12 . The array substrate according to  claim 1 , wherein
 the second sub-line is located in a layer different from the layer in which the main structures of the plurality of data lines are located.   
     
     
         13 . The array substrate according to  claim 12 , comprising:
 at least one gate metal layer located on the first side of the substrate;   a first source-drain metal layer located on a side of the at least one gate metal layer away from the substrate; and   a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate;   wherein the second sub-line is disposed in any gate metal layer, the first power supply signal lines are disposed in the first source-drain metal layer, and the first sub-line and the main structures of the plurality of data lines are disposed in the second source-drain metal layer.   
     
     
         14 . The array substrate according to  claim 4 , further comprising:
 a plurality of first initial signal lines located on the first side of the substrate and located in the display area; the plurality of first initial signal lines each extending in the second direction; wherein   the plurality of first initial signal lines are located in a layer different from a layer in which the second sub-line is located; an orthographic projection, on the substrate, of a first initial signal line passing through a row of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second sub-line passing through the row of sub-pixel regions.   
     
     
         15 . The array substrate according to  claim 14 , further comprising:
 a plurality of second initial signal lines located on the first side of the substrate and located in the display area; the plurality of second initial signal lines each extending in the first direction; wherein   the plurality of second initial signal lines are located in a layer different from the layer in which the plurality of first initial signal lines are located, and the plurality of second initial signal lines are electrically connected to the plurality of first initial signal lines through another via holes; an orthographic projection, on the substrate, of another first sub-line passing through the column of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second initial signal line passing through the column of sub-pixel regions; or   the plurality of second initial signal lines are located in the layer different from the layer in which the plurality of first initial signal lines are located, and the plurality of second initial signal lines are electrically connected to the plurality of first initial signal lines through the another via holes; the orthographic projection, on the substrate, of the another first sub-line passing through the column of sub-pixel regions at least partially overlaps with the orthographic projection, on the substrate, of the second initial signal line passing through the column of sub-pixel regions; the second initial signal lines and the at least one jumper wire are located in the another same layer, and a second initial signal line is located between a jumper wire and a first power supply signal line; the second initial signal line has an avoidance portion bent towards a side where the first power supply signal line is located, and at least a portion of the jumper wire is located within an avoidance space defined by the avoidance portion.   
     
     
         16 . (canceled) 
     
     
         17 . An array substrate, comprising:
 a substrate having a display area and a peripheral area;   a plurality of first power supply signal lines located on a first side of the substrate and located in the display area; wherein the plurality of first power supply signal lines each extend in a first direction and are sequentially arranged in a second direction; the second direction intersects the first direction, and the second direction and the first direction are both parallel to the substrate;   a plurality of data lines located on the first side of the substrate and located in the display area; wherein the plurality of data lines each extend in the first direction and are sequentially arranged in the second direction; a data line is adjacent to a first power supply signal line; and   a plurality of fan-out lines located on the first side of the substrate; wherein a fan-out line includes a first sub-line and a second sub-line; the first sub-line extends in the first direction and extends from the peripheral area to the display area; the second sub-line extends in the second direction and is located in the display area; an end of the second sub-line is electrically connected to the first sub-line, another end of the second sub-line is electrically connected to a single data line of the plurality of data lines, and the second sub-line is insulated from remaining data lines of the plurality of data lines; wherein   main structures of the data lines are located on a side of the first power supply signal lines away from the substrate, and the first sub-line and the main structures of the data lines are disposed in a same layer;   the array substrate has pixel driving circuits in a plurality of rows and a plurality of columns; an orthographic projection, on the substrate, of the first sub-line passing through a column of pixel driving circuits is located between an orthographic projection, on the substrate, of a first power supply signal line passing through the column of pixel driving circuits and an orthographic projection, on the substrate, of a data line passing through the column of pixel driving circuits.   
     
     
         18 . A display panel, comprising:
 the array substrate according to  claim 1 ;   a light-emitting device layer located on a side of the array substrate; and   an encapsulation layer located on a side of the light-emitting device layer away from the array substrate.   
     
     
         19 . A display apparatus, comprising:
 the display panel according to claim  18 ; the peripheral area of the display panel including a lead-out region and a bonding region that are located on a side of the display area, and the bonding region being located on a side of the lead-out region away from the display area;   a flexible circuit board of which an end is bonded in the bonding region; and   a main control circuit board electrically connected to another end of the flexible circuit board.   
     
     
         20 . The array substrate according to  claim 12 , further comprising:
 a plurality of first initial signal lines located on the first side of the substrate and located in the display area; the plurality of first initial signal lines each extending in the second direction; wherein   the plurality of first initial signal lines are located in a layer different from the layer in which the second sub-line is located; an orthographic projection, on the substrate, of a first initial signal line passing through a row of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second sub-line passing through the row of sub-pixel regions.   
     
     
         21 . The array substrate according to  claim 20 , further comprising:
 a plurality of second initial signal lines located on the first side of the substrate and located in the display area; the plurality of second initial signal lines each extending in the first direction; wherein   the plurality of second initial signal lines are located in a layer different from the layer in which the plurality of first initial signal lines are located, and the plurality of second initial signal lines are electrically connected to the plurality of first initial signal lines through via holes; an orthographic projection, on the substrate, of another first sub-line passing through the column of sub-pixel regions at least partially overlaps with an orthographic projection, on the substrate, of a second initial signal line passing through the column of sub-pixel regions.   
     
     
         22 . A display panel, comprising:
 the array substrate according to  claim 17 ;   a light-emitting device layer located on a side of the array substrate; and   an encapsulation layer located on a side of the light-emitting device layer away from the array substrate.   
     
     
         23 . A display apparatus, comprising:
 the display panel according to claim  22 ; the peripheral area of the display panel including a lead-out region and a bonding region that are located on a side of the display area, and the bonding region being located on a side of the lead-out region away from the display area;   a flexible circuit board of which an end is bonded in the bonding region; and   a main control circuit board electrically connected to another end of the flexible circuit board.