Analog-to-digital conversion using differential oscillator techniques

Abstract

An apparatus includes a pair of voltage-controlled oscillators (VCOs). The pair includes a first VCO with a first biasing stage receiving an input voltage signal and a first output stage coupled to the first biasing stage. The first output stage generates a first output frequency signal based on the input voltage signal. The pair also includes a second VCO. The second VCO includes a second biasing stage receiving the input voltage signal and a second output stage coupled to the second biasing stage. The second output stage generates a second output frequency signal based on the input voltage signal.

What is claimed is: 
     
         1 . An apparatus comprising:
 a first biasing circuit comprising:
 a first input stage comprising a plurality of serially coupled N-type metal-oxide semiconductor (NMOS) transistors, the plurality of serially coupled NMOS transistors comprising a corresponding plurality of gate terminals configured to receive an input voltage signal; and 
 a first mirroring stage comprising a plurality of P-type metal-oxide semiconductor (PMOS) transistors, the plurality of PMOS transistors having corresponding source terminals coupled to a voltage common collector (Vcc) rail and configured to generate a first PMOS bias voltage based on the input voltage signal; and 
   a second biasing circuit comprising:
 a second input stage comprising a plurality of serially coupled PMOS transistors, the plurality of serially coupled PMOS transistors comprising a corresponding plurality of gate terminals configured to receive the input voltage signal; and 
 a second mirroring stage comprising a plurality of NMOS transistors, the plurality of PMOS transistors having corresponding drain terminals coupled to a voltage supply source (Vss) rail and configured to generate a first NMOS bias voltage based on the input voltage signal. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the plurality of PMOS transistors of the first mirroring stage comprise a first PMOS transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor of the first mirroring stage having commonly coupled gate terminals. 
     
     
         3 . The apparatus of  claim 1 , wherein one of the plurality of PMOS transistors of the first mirroring stage comprises a drain terminal coupled to a source terminal of one of the plurality of serially coupled NMOS transistors of the first input stage. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 an NMOS biasing transistor, the NMOS biasing transistor comprising a drain terminal coupled to the first input stage.   
     
     
         5 . The apparatus of  claim 4 , wherein the NMOS biasing transistor comprises a source terminal coupled to the first mirroring stage. 
     
     
         6 . The apparatus of  claim 4 , wherein the NMOS biasing transistor is configured to generate a second NMOS bias voltage based on the input voltage signal. 
     
     
         7 . The apparatus of  claim 1 , wherein the plurality of NMOS transistors of the second mirroring stage comprise a first NMOS transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor of the second mirroring stage having commonly coupled gate terminals. 
     
     
         8 . The apparatus of  claim 1 , wherein one of the plurality of NMOS transistors of the second mirroring stage comprises a source terminal coupled to a drain terminal of one of the plurality of serially coupled PMOS transistors of the second input stage. 
     
     
         9 . The apparatus of  claim 1 , further comprising:
 a PMOS biasing transistor, the PMOS biasing transistor comprising a source terminal coupled to the Vcc rail and the second input stage.   
     
     
         10 . The apparatus of  claim 1 , wherein the apparatus comprises one or more interfaces coupled to the first biasing circuit and the second biasing circuit. 
     
     
         11 . The apparatus of  claim 1 , wherein the apparatus comprises one or more interconnects coupling the first biasing circuit and the second biasing circuit. 
     
     
         12 . The apparatus of  claim 1 , wherein the apparatus comprises a processor, and wherein the processor includes the first biasing circuit and the second biasing circuit. 
     
     
         13 . An apparatus comprising:
 a pair of voltage controlled oscillators (VCOs), the pair comprising:
 a first voltage controlled oscillator (VCO), the first VCO comprising a first biasing stage receiving an input voltage signal, and a first output stage coupled to the first biasing stage, the first output stage generating a first output frequency signal based on the input voltage signal; and 
 a second VCO, the second VCO comprising a second biasing stage receiving the input voltage signal, and a second output stage coupled to the second biasing stage, the second output stage generating a second output frequency signal based on the input voltage signal. 
   
     
     
         14 . The apparatus of  claim 13 , wherein the first VCO and the second VCO are coupled to a voltage supply source (Vss) rail associated with a first voltage level and voltage common collector (Vcc) rail associated with a second voltage level. 
     
     
         15 . The apparatus of  claim 14 , wherein the pair of VCOs are configured to operate when the input voltage signal is above the first voltage level and below the second voltage level. 
     
     
         16 . The apparatus of  claim 14 , wherein the first VCO and the second VCO are configured to operate when the input voltage signal is between a first threshold voltage from the first voltage level and a second threshold voltage from the second voltage level. 
     
     
         17 . The apparatus of  claim 16 , wherein the first VCO is activated and the second VCO is deactivated when the input voltage signal is below the first threshold voltage. 
     
     
         18 . The apparatus of  claim 17 , wherein the second VCO is activated and the first VCO is deactivated when the input voltage signal is above the second threshold voltage. 
     
     
         19 . A method comprising:
 detecting, at a common input of a first voltage controlled oscillator (VCO) and a second VCO, an input voltage signal;   determining a voltage level of the input voltage signal, the voltage level being greater than or equal a voltage supply source (Vss) voltage level and smaller than or equal a voltage common collector (Vcc) voltage level; and   activating one or both of the first VCO and the second VCO based on the voltage level.   
     
     
         20 . The method of  claim 19 , further comprising:
 activating the first VCO and deactivating the second VCO when the voltage level of the input voltage signal is below a first threshold voltage from the Vss voltage level;   deactivating the first VCO and activating the second VCO when the voltage level of the input voltage signal is above a second threshold voltage from the Vcc voltage level; and   activating the first VCO and the second VCO when the voltage level of the input voltage signal is between the first threshold voltage and the second threshold voltage.