Metal insulator metal capacitor (mim capacitor)

Abstract

A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry, where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. A semiconductor device including a metal insulator metal capacitor (MIM capacitor), where a bottom electrode of the MIM capacitor includes a plurality of vertical pillars extending up from a bottom layer. Forming back end of line Mx-1 metal line layer, forming a plurality of Vx-1 via on the Mx-1 metal line layer, forming Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via, forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and forming a block mask protecting a portion of the semiconductor device.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device,   wherein a bottom electrode of the MIM capacitor comprises a plurality of vertical pillars extending up from a bottom layer, wherein the plurality of vertical pillars comprises Vx-1 vias and Vx vias.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a top electrode of the MIM capacitor, the top electrode comprising a comb like structure surrounding the plurality of vertical pillars extending up from the bottom layer of the bottom electrode.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 the bottom layer of the bottom electrode is horizontally aligned with an Mx-1 metal layer of the back end of line circuitry.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein
 an upper horizontal surface of the bottom electrode is horizontally aligned with an Mx metal line of the back end of line circuitry.   
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a metal nucleation layer conformally lining upper horizontal and vertical side surfaces of the plurality of vertical pillars of the bottom electrode, wherein   the metal nucleation layer comprises an uneven rough surface which increases a surface area of the bottom electrode.   
     
     
         6 . The semiconductor device according to  claim 5 , further comprising:
 a high-k dielectric on upper horizontal and vertical side surfaces of the metal nucleation layer on the plurality of vertical pillars of the bottom electrode.   
     
     
         7 . The semiconductor device according to  claim 1 , further comprising:
 a bottom electrode contact, wherein   the bottom electrode contact is horizontally aligned with a Vx via above an Mx metal line of the back end of line circuitry.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein
 the bottom electrode comprises ruthenium (Ru) and a top electrode comprises tungsten (W).   
     
     
         9 . A semiconductor device comprising:
 a metal insulator metal capacitor (MIM capacitor),   wherein a bottom electrode of the MIM capacitor comprises a plurality of vertical pillars extending up from a bottom layer.   
     
     
         10 . The semiconductor device according to  claim 9 , further comprising:
 a top electrode of the MIM capacitor, the top electrode comprising a comb like structure surrounding the plurality of vertical pillars extending up from the bottom layer of the bottom electrode.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein
 the bottom electrode comprises ruthenium (Ru) and the top electrode comprises tungsten (W).   
     
     
         12 . The semiconductor device according to  claim 10 , further comprising:
 an upper horizontal surface of the bottom electrode is above a lower horizontal surface of the top electrode.   
     
     
         13 . The semiconductor device according to  claim 9 , further comprising:
 a high-k liner between the bottom electrode and a top electrode.   
     
     
         14 . The semiconductor device according to  claim 9 , further comprising:
 a bottom electrode contact connected to the bottom electrode; and   a top electrode contact connected to the top electrode.   
     
     
         15 . A method of forming a semiconductor device comprising:
 forming back end of line Mx-1 metal line layer;   forming a plurality of Vx-1 via on the Mx-1 metal line layer;   forming a Mx metal line layer with subtractive patterning on the plurality of the Vx-1 via;   forming a plurality of Vx via on the Mx metal line layer with subtractive patterning; and   forming a block mask protecting a portion of the semiconductor device.   
     
     
         16 . The method according to  claim 15 , wherein
 a bottom electrode of a metal insulator metal (MIM) capacitor comprises a plurality of vertical pillars and the Mx-1 metal line layer, wherein   the plurality of vertical pillars comprise a portion not protected by the block mask of the plurality of the Vx-1 via, a portion not protected by the block mask of the Mx metal line and a portion not protected by the block mask of the plurality of the Vx via.   
     
     
         17 . The method according to  claim 16 , further comprising:
 forming a metal nucleation layer conformally lining upper horizontal and vertical side surfaces of the plurality of vertical pillars of the bottom electrode and the Mx-1 metal line layer, wherein   the metal nucleation layer comprises an uneven rough surface which increases a surface area of the bottom electrode.   
     
     
         18 . The method according to  claim 17 , further comprising:
 forming a high-k dielectric on upper horizontal and vertical side surfaces of the metal nucleation layer on the plurality of vertical pillars of the bottom electrode and the Mx-metal line layer of the bottom electrode.   
     
     
         19 . The method according to  claim 18 , further comprising:
 forming a top electrode of the MIM capacitor on the high-k dielectric, the top electrode comprising a complementary comb like structure surrounding the plurality of vertical pillars extending up from the bottom layer of the Mx-1 metal line layer of the bottom electrode.   
     
     
         20 . The method according to  claim 19 , wherein
 the bottom electrode comprises ruthenium (Ru) and the top electrode comprises tungsten (W).