Heat Dissipation Structures

Abstract

The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

What is claimed is: 
     
         1 . A structure, comprising:
 a stack of chip layers;   a dummy region, surrounding the stack of chip layers, comprising:
 a thermal interface material ring comprising a first material having a first thermal conductivity, and 
 a thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity and disposed on the thermal interface material ring; and 
   a thermal interface material layer disposed on the dummy region.   
     
     
         2 . The structure of  claim 1 , wherein a bottom surface of the thermally conductive structure is in contact with a top surface of the thermal interface material ring. 
     
     
         3 . The structure of  claim 1 , wherein the dummy region further comprises a molding compound layer, and
 wherein the thermal interface material ring and the thermally conductive structure are disposed in the molding compound layer.   
     
     
         4 . The structure of  claim 1 , wherein the dummy region further comprises a molding compound layer, and
 wherein the thermal interface material layer is disposed on the molding compound layer.   
     
     
         5 . The structure of  claim 1 , further comprising an other thermally conductive structure disposed along an inner sidewall of the dummy region and in contact with a sidewall of the thermal interface material ring. 
     
     
         6 . The structure of  claim 1 , further comprising a bottom chip layer, wherein the stack of chip layers and the dummy region are disposed on the bottom chip layer. 
     
     
         7 . The structure of  claim 1 , wherein the thermal interface material ring surrounds the stack of chip layers. 
     
     
         8 . The structure of  claim 1 , wherein the thermal interface material ring comprises silver, aluminum nitride, or silicon carbide. 
     
     
         9 . The structure of  claim 1 , wherein the stack of chip layers comprises a stack of memory chips. 
     
     
         10 . The structure of  claim 1 , further comprising a heat sink disposed on the thermal interface material layer. 
     
     
         11 . A structure, comprising:
 an interface layer, comprising:
 a dielectric layer; and 
 a first thermally conductive structure disposed in the dielectric layer; 
   a first die layer, comprising:
 a molding layer disposed on the interface layer; 
 a semiconductor device disposed in the molding layer; 
 a second thermally conductive structure disposed in the molding layer; and 
 a thermal interface material ring disposed on the second thermally conductive 
   structure and in the molding layer; and   a second die layer disposed on the first die layer.   
     
     
         12 . The structure of  claim 11 , further comprising a thermal interface layer disposed on the second die layer. 
     
     
         13 . The structure of  claim 11 , wherein the first and second thermally conductive structures are in contact with each other. 
     
     
         14 . The structure of  claim 11 , wherein the first thermally conductive structure comprises:
 a metal core; and   a dielectric liner surrounding the metal core.   
     
     
         15 . The structure of  claim 11 , wherein the first thermally conductive structure comprises:
 a metal core;   a dielectric liner surrounding the metal core; and   metallic particles disposed in the dielectric liner.   
     
     
         16 . The structure of  claim 11 , wherein the first and second thermally conductive structures comprise tapered cross-sectional profiles. 
     
     
         17 . A method, comprising:
 stacking a first chip on a second chip;   forming a thermal interface ring surrounding the first and second chips;   forming a thermally conductive structure on the thermal interface ring; and   depositing a molding compound to encapsulate the thermal interface ring and the thermally conductive structure.   
     
     
         18 . The method of  claim 17 , wherein forming the thermal interface ring comprises depositing a layer of silver, aluminum nitride or silicon carbide. 
     
     
         19 . The method of  claim 17 , wherein forming the thermally conductive structure comprises:
 depositing a sacrificial layer on the thermal interface ring; and   forming the thermally conductive structure in the sacrificial layer.   
     
     
         20 . The method of  claim 17 , wherein forming the thermal interface ring comprises depositing a thermal interface material with a thickness between about 0.3 mm and about 0.8 mm.