Over current protection circuit arranged for providing an over current signal, as well as a corresponding method and computer program product

Abstract

An over current protection circuit arranged for providing an over current signal, the over current protection circuit includes a compare stage arranged for determining that a blanking time value is higher than a predefined reference value, an output stage arranged for outputting the over current signal based on the determination, a blanking time stage arranged for generating the blanking time value, and the blanking time stage is arranged to start generating the blanking time value upon a load current exceeding a predefined set current, the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.

1 . An over current protection circuit arranged for providing an over current signal, the over current protection circuit comprising:
 a compare stage arranged for determining that a blanking time value is higher than a predefined reference value;   an output stage arranged for outputting the over current signal based on the determination; and   a blanking time stage arranged for generating the blanking time value, wherein the blanking time stage is arranged to start generating the blanking time value upon a load current exceeding a predefined set current,   wherein the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.   
     
     
         2 . The over current protection circuit in accordance with  claim 1 , wherein the blanking time stage is arranged to modulate the blanking time value so that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current. 
     
     
         3 . The over current protection circuit in accordance with  claim 1 , wherein the blanking time stage is arranged to module the blanking time value so that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current. 
     
     
         4 . The over current protection circuit in accordance with  claim 1 , wherein the blanking time stage comprises:
 a timer capacitor arranged for storing energy;   a first current source arranged for charging the timer capacitor;   a current provided by the first current source that is proportional to the predefined set current;   a second current source arranged for discharging the timer capacitor;   a current provided by the second current source is proportional to the load current; and   an output of the timer capacitor is connected to the compare stage.   
     
     
         5 . The over current protection circuit in accordance with  claim 4 , wherein the blanking time stage further comprises:
 a third current source for discharging the timer capacitor, wherein the third current source has a current provided that is constant.   
     
     
         6 . The over current protection circuit in accordance with  claim 4 , wherein the compare stage comprises:
 a first comparator having an inverting input and a non-inverting input, wherein the inverting input of the first comparator is connected to the output of the timer capacitor, and the non-inverting output of the first comparator is connected to the predefined reference value.   
     
     
         7 . The over current protection circuit in accordance with  claim 5 , wherein the compare stage further comprises:
 a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current,   wherein the output stage comprises:   an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.   
     
     
         8 . The over current protection circuit in accordance with  claim 7 , wherein the blanking time stage further comprises:
 a switch connected in series with the third current source for activating, and deactivating, the third current source, and   wherein the switch is controlled by the output of the second comparator.   
     
     
         9 . A method for providing an over current signal using an over current protection circuit in accordance with  claim 1 , wherein the method comprises the steps of:
 determining, by the compare stage, that a blanking time value is higher than a predefined reference value;   outputting, by the output stage, the over current signal based on the determination; and   generating, by the blanking time stage, the blanking time value, wherein the blanking time value is started to be generated upon a load current exceeding a predefined set current,   wherein the step of generating comprises modulating the blanking time value based on a magnitude in which the load current exceeds the predefined set current.   
     
     
         10 . The method in accordance with  claim 9 , wherein the step of modulating further comprises:
 modulating the blanking time value so that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current.   
     
     
         11 . The method in accordance with  claim 9 , wherein the step of modulating further comprises:
 modulating the blanking time value so that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current.   
     
     
         12 . The method in accordance with  claim 9 , wherein the blanking time stage comprises:
 a timer capacitor arranged for storing energy;   a first current source arranged for charging the timer capacitor;   a current provided by the first current source is proportional to the predefined set current;   a second current source arranged for discharging the timer capacitor;   a current provided by the second current source is proportional to the load current; and   an output of the timer capacitor is connected to the compare stage.   
     
     
         13 . The method in accordance with  claim 10 , wherein the blanking time stage comprises:
 a timer capacitor arranged for storing energy;   a first current source arranged for charging the timer capacitor;   a current provided by the first current source is proportional to the predefined set current;   a second current source arranged for discharging the timer capacitor;   a current provided by the second current source is proportional to the load current; and   an output of the timer capacitor is connected to the compare stage.   
     
     
         14 . The method in accordance with  claim 12 , wherein the blanking time stage further comprises:
 a third current source for discharging the timer capacitor, wherein the third current source provides a current that is constant.   
     
     
         15 . The method in accordance with  claim 12 , wherein the compare stage comprises:
 a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value;   a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current;   a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator;   wherein the output stage comprises:   an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.   
     
     
         16 . The method in accordance with  claim 14 , wherein the compare stage comprises:
 a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value;   a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current;   a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator;   wherein the output stage comprises:   an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.   
     
     
         17 . A computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with  claim 9 . 
     
     
         18 . A computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with  claim 10 .