Integrated circuit device

Abstract

The inventive concept provides an integrated circuit device including: a substrate including a cell region and a peripheral circuit region; a plurality of bit line structures spaced apart from each other in the cell region with each bit line structure including a bit line conductive layer and a bit line capping layer on the bit line conductive layer; and a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective bit line structure of the plurality of bit line structures and electrically connected to the substrate, wherein the peripheral circuit region includes a gate structure and a core capping layer on the gate structure; a direct contact plug extending vertically with respect to the substrate; first peripheral circuit wiring patterns extending laterally and spaced apart from each other on a first plane at a first vertical level relative to the substrate; and second peripheral circuit wiring patterns extending laterally and spaced apart from each other on a second plane at a second vertical level relative to the substrate, wherein the second vertical level is different from the first vertical level.

What is claimed is: 
     
         1 . An integrated circuit device comprising:
 a substrate comprising a cell region and a peripheral circuit region;   a plurality of bit line structures spaced apart from each other in the cell region with each bit line structure comprising a bit line conductive layer and a bit line capping layer on the bit line conductive layer; and   a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective bit line structure of the plurality of bit line structures and electrically connected to the respective bit line structure,   wherein the peripheral circuit region comprises a gate structure and a core capping layer on the gate structure;   a direct contact plug extending vertically with respect to the substrate;   first peripheral circuit wiring patterns extending laterally and spaced apart from each other on a first plane at a first vertical level relative to the substrate; and   second peripheral circuit wiring patterns extending laterally and spaced apart from each other on a second plane at a second vertical level relative to the substrate, wherein the second vertical level is different from the first vertical level.   
     
     
         2 . The integrated circuit device according to  claim 1 , wherein the first plane and the second plane are each parallel to the substrate. 
     
     
         3 . The integrated circuit device according to  claim 1 , wherein a height of the second vertical level is greater than a height of the first vertical level. 
     
     
         4 . The integrated circuit device according to  claim 1 , wherein the first vertical level is at the same vertical level as the plurality of landing pads relative to a main surface of the substrate. 
     
     
         5 . The integrated circuit device according to  claim 1 , further comprising an insulating material separating the first peripheral circuit wiring patterns from the second peripheral circuit wiring patterns. 
     
     
         6 . The integrated circuit device according to  claim 5 , further comprising an insulating layer on the plurality of landing pads, wherein:
 the insulating layer is formed of silicon nitride; and   the second peripheral circuit wiring patterns are formed of the same material as the first peripheral circuit wiring patterns.   
     
     
         7 . The integrated circuit device according to  claim 1 , wherein at least a portion of at least one of the first peripheral circuit wiring patterns is electrically connected to the direct contact plug. 
     
     
         8 . The integrated circuit device according to  claim 7 , wherein a lower surface of the first peripheral circuit wiring pattern is at the same vertical level as an upper surface of the direct contact plug. 
     
     
         9 . The integrated circuit device according to  claim 1 , further comprising a via electrically connecting at least a portion of the second peripheral circuit wiring patterns to the direct contact plug. 
     
     
         10 . The integrated circuit device according to  claim 1 , wherein a height of the uppermost surface of the peripheral circuit region is greater than a height of the uppermost surface of the cell region. 
     
     
         11 . The integrated circuit device according to  claim 10 , wherein a difference between the height of the uppermost surface of the peripheral circuit region and the height of the uppermost surface of the cell region is the same as the thickness of the second peripheral circuit wiring patterns. 
     
     
         12 . An integrated circuit device comprising:
 a substrate comprising a cell region and a peripheral circuit region;   a plurality of bit line structures extending parallel to each other in a first horizontal direction in the cell region;   a plurality of buried contacts electrically connected to the cell region with each buried contact of the plurality of buried contacts filling a portion of a space between respective adjacent bit line structures of the plurality of bit line structures;   a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective buried contact of the plurality of buried contacts;   a gate structure and a direct contact plug that are arranged in the peripheral circuit region;   a first peripheral circuit wiring pattern at a vertical level that is higher relative to the substrate than an uppermost surface of the gate structure and having a plurality of first peripheral circuit wiring pattern recesses;   an insulating layer filling the plurality of first peripheral circuit wiring pattern recesses and covering an upper portion of the first peripheral circuit wiring pattern; and   a second peripheral circuit wiring pattern formed on the insulating layer.   
     
     
         13 . The integrated circuit device according to  claim 12 , wherein at least a portion of the first peripheral circuit wiring pattern is electrically connected to the direct contact plug. 
     
     
         14 . The integrated circuit device according to  claim 13 , wherein a lower surface of the first peripheral circuit wiring pattern is at the same vertical level as an upper surface of the direct contact plug. 
     
     
         15 . The integrated circuit device according to  claim 12 , further comprising a via electrically connecting at least a portion of the second peripheral circuit wiring pattern to the direct contact plug. 
     
     
         16 . The integrated circuit device according to  claim 12 , further comprising a plurality of capacitor structures, each comprising a lower electrode electrically connected to a respective landing pad of the plurality of landing pads, an upper electrode, and a capacitor dielectric layer interposed between the lower electrode and the upper electrode. 
     
     
         17 . The integrated circuit device according to  claim 12 , wherein an upper surface of the first peripheral circuit wiring pattern is at the same vertical level as an upper surface of the plurality of landing pads relative to a main surface of the substrate. 
     
     
         18 . An integrated circuit device comprising: 
       a substrate comprising a cell region having a first active region and a peripheral circuit region having a second active region;
 a direct contact contacting the first active region in the cell region; 
 a bit line structure on the direct contact; 
 a capacitor structure electrically connected to the first active region; 
 a gate structure on the second active region in the peripheral circuit region; 
 a first peripheral circuit wiring pattern adjacent to the gate structure and electrically connected to the second active region; 
 a second peripheral circuit wiring pattern on the first peripheral circuit wiring pattern; 
 a wiring insulating layer between the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern; and 
 a contact plug penetrating the wiring insulating layer and connected to at least one of the first peripheral circuit wiring pattern and the second peripheral circuit wiring pattern, 
 wherein the wiring insulating layer extends into the cell region, and 
 the capacitor structure comprises a dummy electrode that contacts an upper surface of the wiring insulating layer. 
 
     
     
         19 . The integrated circuit device according to  claim 18 , wherein:
 a vertical level of an uppermost surface of the first peripheral circuit wiring pattern is lower than a vertical level of a lowermost surface of the second peripheral circuit wiring pattern relative to the substrate, and   the second peripheral circuit wiring pattern is formed of the same material as the first peripheral circuit wiring pattern.   
     
     
         20 . The integrated circuit device according to  claim 18 , wherein the wiring insulating layer is formed such that an upper surface of the first peripheral circuit wiring pattern is not physically exposed to an external surface of the integrated circuit device.