Thermally conductive spacer

Abstract

A thermally conductive spacer is positioned between two semiconductor dies in a stack of semiconductor dies. The spacer includes thermal conductivity features that dissipate heat or otherwise conduct heat away from the semiconductor dies in the stack. The spacer may have dimensions that are larger than the dimensions of the semiconductor dies in the stack. The thermal conductivity features of the spacer, in addition to the larger dimensions, enable the spacer to effectively dissipate heat from, and improve a thermal profile of, the stack of semiconductor dies.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a printed circuit board (PCB);   a first stack of semiconductor dies;   a second stack of semiconductor dies; and   a thermally conductive spacer provided between the first stack of semiconductor dies and the second stack of semiconductor dies, the thermally conductive spacer comprising:
 a thermal conductivity feature that moves heat generated by the semiconductor dies adjacent to the thermally conductive spacer away from the adjacent semiconductor dies. 
   
     
     
         2 . The semiconductor package of  claim 1 , wherein a set of dimensions of the thermally conductive spacer are greater than a set of dimensions of at least one semiconductor die associated with the first stack of semiconductor dies. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the thermal conductivity feature comprises a thermal conductive material provided on one or more of a top surface of the thermally conductive spacer and a bottom surface of the thermally conductive spacer. 
     
     
         4 . The semiconductor package of  claim 3 , wherein the thermal conductive material is arranged in a grid pattern. 
     
     
         5 . The semiconductor package of  claim 1 , wherein the thermal conductivity feature comprises one or more vias provided at least partially thorough the thermally conductive spacer. 
     
     
         6 . The semiconductor package of  claim 5 , wherein the one or more vias are filled with a thermal conductive material. 
     
     
         7 . The semiconductor package of  claim 1 , further comprising one or more tines extending from a surface of the thermally conductive spacer to a surface of the PCB. 
     
     
         8 . The semiconductor package of  claim 7 , wherein the one or more tines extend from the surface of the thermally conductive spacer to a cover associated with the semiconductor package. 
     
     
         9 . The semiconductor package of  claim 1 , wherein at least one of the first stack of semiconductor dies and the second stack of semiconductor dies is a stack of NAND memory dies. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the thermally conductive spacer is comprised of a thermal conductive material. 
     
     
         11 . A semiconductor package, comprising:
 a printed circuit board (PCB);   a stack of memory dies, each memory die of the stack of memory dies having a first set of dimensions; and   a thermally conductive spacer provided between a first memory die of the stack of memory dies and a second memory die of the stack of memory dies, the thermally conductive spacer having a thermal conductivity feature and having a second set of dimensions that are larger than the first set of dimensions.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the thermal conductivity feature comprises a thermal conductive material provided on one or more of a top surface of the thermally conductive spacer and a bottom surface of the thermally conductive spacer. 
     
     
         13 . The semiconductor package of  claim 11 , wherein the thermal conductivity feature comprises one or more vias provided at least partially thorough the thermally conductive spacer. 
     
     
         14 . The semiconductor package of  claim 13 , wherein the one or more vias are filled with a thermal conductive material. 
     
     
         15 . The semiconductor package of  claim 11 , further comprising one or more pads provided on an exposed surface of the thermally conductive spacer. 
     
     
         16 . The semiconductor package of  claim 15 , further comprising one or more tines extending from the one or more pads provided on the exposed surface of the thermally conductive spacer. 
     
     
         17 . The semiconductor package of  claim 16 , wherein the one or more tines extend from the surface of the thermally conductive spacer to the PCB. 
     
     
         18 . The semiconductor package of  claim 16 , wherein the one or more tines extend from the surface of the thermally conductive spacer to a cover associated with the semiconductor package. 
     
     
         19 . A semiconductor package, comprising:
 a first stack of integrated circuit means;   a second stack of integrated circuit means;   a thermally conductive spacing means provided between the first stack of integrated circuit means and the second stack of integrated circuit means, the thermally conductive spacing means comprising:
 a thermal conductivity means; and 
 a set of dimensions that are greater than a set of dimensions of at least one integrated circuit means in the first stack of integrated circuit means. 
   
     
     
         20 . The semiconductor package of  claim 19 , wherein the thermal conductivity means is provided on one or more of a top surface of the thermally conductive spacing means and a bottom surface of the thermally conductive spacing means.