Semiconductor memory device and method of fabricating the same

Abstract

A semiconductor device includes a device isolation pattern defining active portions extending in a first direction, a first bit line intersecting the active portions in a second direction, a second bit line spaced apart from the first bit line in a third direction, bit line capping patterns on the bit lines, a storage node contact between the bit lines, a diffusion barrier layer on sidewalls of bit lines and on a top of the storage node contact, and a landing pad on the diffusion barrier layer. A first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the bit line capping patterns, and a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end.

1 . A semiconductor memory device comprising:
 a substrate having active portions extending in a first direction, the active portions comprising first and second impurity regions at central and edge portions thereof, respectively;   a device isolation pattern in the substrate between the active portions;   a first bit line connected to at least one of the first impurity regions and extending over the active portions in a second direction that intersects the first direction;   a second bit line spaced apart from the first bit line in a third direction that intersects the first and second directions;   first and second bit line capping patterns on the first and second bit lines, respectively;   a storage node contact between the first bit line and the second bit line and in contact with one of the second impurity regions;   a diffusion barrier layer on a sidewall of the first bit line, on a sidewall of the second bit line, and on an upper surface of the storage node contact therebetween; and   a landing pad on the diffusion barrier layer,   wherein a first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the first bit line capping pattern, relative to the substrate, and   wherein a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end, relative to the substrate.   
     
     
         2 . The semiconductor memory device of  claim 1 , further comprising a spacer structure between the first bit line and the diffusion barrier layer,
 wherein the spacer structure comprises:   a first spacer on the sidewall of the first bit line and on a sidewall of the first bit line capping pattern,   a second spacer on a lower side surface of the first spacer, wherein an upper side surface of the first spacer is free of the second spacer,   a third spacer on a side surface of the second spacer; and   a fourth spacer on the upper side surface of the first spacer and in contact with an upper surface of the second spacer,   wherein an upper end of the second spacer is lower than the first upper end of the diffusion barrier layer, relative to the substrate.   
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the landing pad comprises:
 a first pad portion on the diffusion barrier layer; and   a second pad portion on the first pad portion and in contact with the first bit line capping pattern,   wherein the first pad portion comprises chlorine atoms, and the second pad portion is free of chlorine atoms.   
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the first pad portion comprises first metal grains having a first average size, and
 wherein the second pad portion comprises second metal grains having a second average size smaller than the first average size.   
     
     
         5 . The semiconductor memory device of  claim 3 , wherein the second pad portion extends between an upper sidewall of the first pad portion and the first bit line capping pattern. 
     
     
         6 . The semiconductor memory device of  claim 3 , wherein the first upper end of the diffusion barrier layer extends between the second pad portion and the first bit line capping pattern. 
     
     
         7 . The semiconductor memory device of  claim 1 , wherein the landing pad comprises:
 a first pad portion on the diffusion barrier layer; and   a second pad portion on the first pad portion and in contact with the first bit line capping pattern,   wherein the first pad portion and the second pad portion comprise a first concentration of chlorine atoms and a second concentration of chlorine atoms, respectively, and   wherein the first concentration is different from the second concentration.   
     
     
         8 . The semiconductor memory device of  claim 1 , wherein the first upper end of the diffusion barrier layer has a substantially planar or concave upper surface. 
     
     
         9 . A semiconductor memory device comprising:
 a substrate having active portions that extend in a first direction, the active portions comprising first and second impurity regions at central and edge portions thereof, respectively;   a device isolation pattern in the substrate between the active portions;   a first bit line connected to at least one of the first impurity regions and extending over the active portions in a second direction that intersects the first direction;   a second bit line spaced apart from the first bit line in a third direction that intersects the first and second directions;   first and second bit line capping patterns on the first and second bit lines, respectively;   a storage node contact between the first bit line and the second bit line and in contact with one of the second impurity regions;   a diffusion barrier layer on a sidewall of the first bit line, on a sidewall of the second bit line, and on an upper surface of the storage node contact therebetween, wherein upper sidewalls of the first and second bit line capping patterns are free of the diffusion barrier layer; and   a landing pad on the diffusion barrier layer,   wherein the landing pad comprises:   a first pad portion on the diffusion barrier layer; and a second pad portion on the first pad portion and in contact with the first bit line capping pattern,   wherein the first pad portion comprises chlorine atoms, and   wherein the second pad portion is free of chlorine atoms.   
     
     
         10 . The semiconductor memory device of  claim 9 ,
 wherein a first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the first bit line capping pattern, relative to the substrate, and   wherein a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end, relative to the substrate.   
     
     
         11 . The semiconductor memory device of  claim 10 , further comprising a spacer structure between the first bit line and the diffusion barrier layer,
 wherein the spacer structure comprises:   a first spacer on the sidewall of the first bit line and on a sidewall of the first bit line capping pattern;   a second spacer on a lower side surface of the first spacer, wherein an upper side surface of the first spacer is free of the second spacer;   a third spacer on a side surface of the second spacer; and   a fourth spacer on the upper side surface of the first spacer and in contact with an upper surface of the second spacer,   wherein an upper end of the second spacer is lower than the first upper end of the diffusion barrier layer, relative to the substrate.   
     
     
         12 . The semiconductor memory device of  claim 9 , wherein the first pad portion comprises first metal grains having a first average size, and
 wherein the second pad portion comprises second metal grains having a second average size smaller than the first average size.   
     
     
         13 . The semiconductor memory device of  claim 9 , wherein the second pad portion extends between an upper sidewall of the first pad portion and the first bit line capping pattern. 
     
     
         14 . The semiconductor memory device of  claim 9 , wherein the diffusion barrier layer extends between the second pad portion and the first bit line capping pattern. 
     
     
         15 . The semiconductor memory device of  claim 9 , wherein an upper surface of the diffusion barrier layer is substantially planar or concave. 
     
     
         16 . A semiconductor memory device comprising:
 a substrate having active portions extending in a first direction, the active portions comprising first and second impurity regions at central and edge portions thereof, respectively;   a device isolation pattern in the substrate between the active portions;   word lines in the substrate and intersecting the active portions in a second direction that intersects the first direction;   word line capping patterns on the word lines;   a first bit line connected to at least one of the first impurity region and extending over the word lines in a third direction that intersects the first and second directions;   a second bit line spaced apart from the first bit line in the second direction;   first and second bit line capping patterns on the first and second bit lines, respectively;   a storage node contact between the first bit line and the second bit line and in contact with one of the second impurity regions;   a diffusion barrier layer on a sidewall of the first bit line, on a sidewall of the second bit line, and on an upper surface of the storage node contact therebetween, wherein upper sidewalls of the first and second bit line capping patterns are free of the diffusion barrier layer; and   a landing pad on the diffusion barrier layer,   wherein the landing pad comprises:   a first pad portion on the diffusion barrier layer; and   a second pad portion on the first pad portion and in contact with the first bit line capping pattern;   wherein the first pad portion comprises first metal grains having a first average size, and   wherein the second pad portion comprises second metal grains having a second average size smaller than the first average size.   
     
     
         17 . The semiconductor memory device of  claim 16 , wherein the first pad portion comprises chlorine atoms, and
 wherein the second pad portion is free of chlorine atoms.   
     
     
         18 . The semiconductor memory device of  claim 16 ,
 wherein a first upper end of the diffusion barrier layer on the sidewall of the first bit line is lower than the first bit line capping pattern, relative to the substrate, and   wherein a second upper end of the diffusion barrier layer on the sidewall of the second bit line is lower than the first upper end, relative to the substrate.   
     
     
         19 . The semiconductor memory device of  claim 18 , further comprising a spacer structure between the first bit line and the diffusion barrier layer,
 wherein the spacer structure comprises:   a first spacer on the sidewall of the first bit line and on a sidewall of the first bit line capping pattern;   a second spacer on a lower side surface of the first spacer, wherein an upper side surface of the first spacer is free of the second spacer;   a third spacer on a side surface of the second spacer; and   a fourth spacer on the upper side surface of the first spacer and in contact with an upper surface of the second spacer,   wherein an upper end of the second spacer is lower than the first upper end of the diffusion barrier layer, relative to the substrate.   
     
     
         20 . The semiconductor memory device of  claim 16 , wherein an upper surface of the diffusion barrier layer is substantially planar or concave. 
     
     
         21 - 23 . (canceled)