Communication Processor Handling Communications Protocols on Separate Threads

Abstract

A multi-thread communication system has several communications processors operative over a single interface for transmitting and receiving packets. The multi-thread communications processor is operative to sequentially handle multiple thread processes for each communications processor on a cycle by cycle basis according to a thread map register which determines the order of execution and how many cycles of a particular thread occur during a canonical interval.

1 - 21 . (canceled) 
     
     
         22 . A communication system comprising:
 a multi-thread processor having stages forming a single execution pipeline and configured to execute a plurality of threads, each thread being executed according to a programmable thread map register identifying a particular thread to fetch an instruction on each successive instruction cycle, the programmable thread map register having a greater number of entries than a number of the plurality of threads;   a first communications processor operative to receive and transmit wireless packets compatible with a first communication protocol;   a first thread of the plurality of threads configured to perform data operations on the first communication processor with an external interface, the external interface having a first response latency associated with the first communications processor;   a second communications processor operative to receive and transmit wireless packets compatible with a second communication protocol;   a second thread of the plurality of threads operative to perform data operations on the second communication processor with the external interface, the external interface having a second response latency associated with the second communications processor;   the programmable thread map register comprising a canonical sequence of programmable thread_id values, the number of unique thread_id values in the canonical sequence being less than a number of thread_id values in the canonical sequence of thread_id values in the programmable thread map register;   where a particular thread_id value for the first thread or the second thread is separated in the thread map register from other particular thread_id values by a number of thread map register entries corresponding to a time delay which is greater than the first response latency or the second response latency.   
     
     
         23 . The s system of  claim 22  where each thread_id is associated with a respective program counter, each said respective program counter identifying an address of an instruction to fetch. 
     
     
         24 . The system of  claim 22  where at least one of the first communications processor and the second communications processor each comprise an antenna, signal processing electronics, and a media access controller (MAC) coupled to the data interface for received packets and packets to transmit. 
     
     
         25 . The communication system of  claim 22  configured to execute at least one process thread servicing a media access controller for the first communications processor and also at least one process thread servicing a media access controller for the second communications processor. 
     
     
         26 . The communication system of  claim 22  where only thread_id values of threads associated with active communication interfaces are present in the thread map register. 
     
     
         27 . The communication system of  claim 26  where the active communication interfaces are switched between an active state and an inactive state during mutually exclusive intervals. 
     
     
         28 . The communication system of  claim 22  where the multi-thread processor also executes a thread map management process increasing the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor. 
     
     
         29 . The communication system of  claim 22  where at least one of the first communication protocol or the second communication protocol is at least one of: a Wireless Local Area Network (WLAN) protocol, a Bluetooth protocol, a Long Term Evolution (LTE) protocol, a fourth generation (4G) telephony protocol, or a Zigbee protocol. 
     
     
         30 . The communication system of  claim 29  where the first communication protocol and second communication protocol are different protocols. 
     
     
         31 . The communication system of  claim 30  where the first communication protocol is a Wireless Local Area Network protocol compatible with an 802.11 IEEE standard and the second communication protocol is a Bluetooth protocol. 
     
     
         32 . The communication system of  claim 22  where at least one of the first communications processor or second communications processor has a receive processor which comprises, in sequence, an antenna, a low noise amplifier, a mixer, a low pass filter, and an analog to digital converter and baseband processor coupled to the media access controller. 
     
     
         33 . The communication system of  claim 22  where at least one of the first communications processor or the second communications processor includes a transmitter coupled to the media access controller, the transmitter further comprising a baseband processor generating a baseband stream of symbols coupled to a mixer for conversion to an RF frequency, the mixer output coupled in sequence to an amplifier, transmit/receive switch, and an antenna. 
     
     
         34 . The communication system of  claim 22  where the first communications processor and the second communications processor are coupled to the multi-thread processor through a single physical interface. 
     
     
         35 . The communication system of  claim 22  where the external interface is at least one of Peripheral Component Interconnect (PCI), Serial Peripheral Interface (SPI), Secure Digital (SD) interface, or an interface providing an address and data to be read or written. 
     
     
         36 . A communication system comprising:
 a multi-thread processor having stages forming a single execution pipeline and configured to execute a plurality of threads, each thread having a unique thread_id, each thread being executed according to a programmable thread map register identifying a particular thread to execute on each successive instruction cycle, the programmable thread map register having a greater number of entries than a number of the plurality of threads;   a plurality of communications processors, each communications processor operative to receive and transmit wireless packets compatible with a respective communication protocol;   each communications processor of the plurality of communications processors having a respective thread of the plurality of threads configured to perform data operations on the respective communications processor with an external interface, the external interface having a response latency;   the programmable thread map register comprising a canonical sequence of the respective thread_id values, the number of unique thread_id values in the canonical sequence being less than a number of thread_id values in the canonical sequence of programmable thread_id values;   where a particular thread_id value for a respective thread is separated in the thread_id register from other particular thread_id values by a number of thread map register entries corresponding to a time delay which is greater than the external interface response latency.   
     
     
         37 . The communication system of  claim 36  where at least one communications processor is operative to transmit and receive wireless local area network (WLAN) packets, the communications processor having a media access controller for the transmission and reception of data using the data interface. 
     
     
         38 . The communication system of  claim 36  where at least one communications processor is operative to transmit and receive Bluetooth Packets. 
     
     
         39 . The communication system of  claim 36  where at least one thread has associated thread_id values which are not in contiguous thread map register locations. 
     
     
         40 . A process for a communication system comprising:
 a multi-thread processor having stages forming a single execution pipeline and configured to execute a plurality of threads, each thread having a unique thread_id, each thread being executed according to a programmable thread map register identifying a particular thread to execute on each successive instruction cycle, the programmable thread map register having a greater number of entries than a number of the plurality of threads;   a plurality of communications processors, each communications processor operative to receive and transmit wireless packets compatible with a respective communication protocol;   each communications processor of the plurality of communications processors having a respective thread of the plurality of threads configured to perform data operations on the respective communications processor with an external interface, the external interface having a response latency;   the programmable thread map register comprising a canonical sequence of the respective thread_id values, the number of unique thread_id values in the canonical sequence being less than a number of thread_id values in the canonical sequence of programmable thread_id values;   the process comprising:   arranging the thread map register such that a particular thread_id value for a respective thread is separated in the thread_id register from other particular thread_id values by a number of thread map register entries corresponding to a time delay which is greater than the external interface response latency.   
     
     
         41 . The process of  claim 40  where the plurality of process threads includes at least one process thread servicing a media access controller for a communications processor. 
     
     
         42 . The process of  claim 40  where at least one thread of the plurality of threads increases the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor.