Semiconductor device

Abstract

The semiconductor device according to one or more embodiments includes a first semiconductor region of a first conductivity type, a second semiconductor region of the second conductivity type formed on the first semiconductor region, and a semiconductor region containing a first trench structure in which a gate electrode is formed via an insulating film on the second semiconductor region, a third semiconductor region of the second conductivity type provided electrically connected to the second semiconductor region in a planar view, and a gate resistance region including a second trench structure in which a gate resistor is formed via an insulating film on the third semiconductor region. The depth of the third semiconductor region is deeper than the depth of the second semiconductor region and shallower than the trench depth of the second trench structure.

1 . A semiconductor device, comprising:
 a first semiconductor region of a first conductivity type;   a second semiconductor region of a second conductivity type formed on the first semiconductor region;   a semiconductor region having a first trench structure in which a gate electrode is formed via a first insulating film on the second semiconductor region;   a third semiconductor region of the second conductivity type arranged so as to be electrically connected to the second semiconductor region outside the semiconductor region; and   a gate resistance region having a second trench structure in which a gate resistor is formed via a second insulating film on the third semiconductor region, wherein
 a depth of the third semiconductor region is deeper than a depth of the second semiconductor region, and 
 the depth of the third semiconductor region is shallower than a trench depth of the second trench structure. 
   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 a trench depth of the first trench structure and the trench depth of the second trench structure are substantially equal.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 a trench spacing of the first trench structure and a trench spacing of the second trench structure are substantially equal.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 a trench width of the first trench structure and a trench width of the second trench structure are substantially equal.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 a trench spacing of the second trench structure is wider than a trench spacing of the first trench structure.   
     
     
         6 . The semiconductor device according to  claim 1 , further comprising:
 in a planar point of view, a voltage resistance improvement region arranged outside the semiconductor region, the voltage resistance improvement region comprises:   the third semiconductor region;   a third trench structure formed to penetrate the third semiconductor region;   a third insulating film placed in the third trench structure; and   a first floating electrode formed via the third insulating film.   
     
     
         7 . The semiconductor device according to  claim 1 , further comprising:
 a fourth trench structure placed around the gate resistance region and penetrating the third semiconductor region around the second trench structure, wherein   the fourth trench structure comprises a second floating electrode through an insulating film inside a trench.   
     
     
         8 . The semiconductor device according to  claim 1 , further comprising:
 a plurality of second trench structures arranged on the semiconductor region, wherein   at least one second trench structure of the plurality of second trench structures is electrically connected to a gate runner via a first contact, and electrically connected to a gate pad at a distance from the first contact via a second contact; and   at least one second trench structure of the plurality of second trench structures is electrically connected to only one of the gate runner or the gate pad via a third contact.   
     
     
         9 . The semiconductor device according to  claim 1 , further comprising:
 a fourth semiconductor region of the first conductivity type placed in contact with the first insulating film on the second semiconductor region; and   a first electrode connected to the second semiconductor region and the fourth semiconductor region, wherein   the first electrode is electrically connected to the third semiconductor region.   
     
     
         10 . The semiconductor device according to  claim 1 , further comprising
 in a planar view, a gate pad electrically connected to the gate resistance region between the semiconductor region and the gate resistance region.   
     
     
         11 . The semiconductor device according to  claim 1 , wherein
 an extending direction of the first trench structure and an extending direction of the second trench structure are substantially parallel.   
     
     
         12 . The semiconductor device according to  claim 8 , wherein
 a plurality of the first trench structures and the plurality of the second trench structures are arranged on the semiconductor region,   an extending direction of the first trench structures and an extending direction of the second trench structures are nonparallel to each other, and   a direction of a portion of the gate runner to which a plurality of gate resistors are connected via contacts and a direction of the portion of the gate runner connected to a plurality of gate electrodes are different.   
     
     
         13 . The semiconductor device according to  claim 1 , further comprising:
 a fourth semiconductor region of the first conductivity type arranged in contact with the first insulating film on the second semiconductor region; and   a first electrode connected to the second semiconductor region and the fourth semiconductor region, wherein   the semiconductor device comprises a plurality of second trench structures, and at least one of the second trench structures comprises:
 a first contact electrically connected with a gate runner; 
 a second contact that is separated from the first contact and electrically connected to a gate pad; and 
 at least one of the second trench structures comprises a fourth contact that is electrically connected to the first electrode. 
   
     
     
         14 . The semiconductor device according to  claim 8 , further comprising:
 a fourth semiconductor region of the first conductivity type placed in contact with the first insulating film on the second semiconductor region; and   a first electrode connected to the second semiconductor region and the fourth semiconductor region, wherein   at least one of the second trench structures comprises a fourth contact that is electrically connected to the first electrode.   
     
     
         15 . A semiconductor device, comprising:
 a first semiconductor region of a first conductivity type;   a second semiconductor region of a second conductivity type formed on the first semiconductor region;   a semiconductor region comprising a first trench structure in which a gate electrode is formed via a first insulating film on the second semiconductor region;   a third semiconductor region of the second conductivity type provided and electrically connected to the second semiconductor region outside the semiconductor region in a planar view; and   a gate resistance region comprising a plurality of second trench structures comprising polysilicon that is insulated from the third semiconductor region, wherein   a depth of the third semiconductor region is deeper than a depth of the second semiconductor region, and   the depth of the third semiconductor region is shallower than a trench depth of the second trench structures.   
     
     
         16 . The semiconductor device according to  claim 15 , wherein
 at least one of the second trench structures comprises:
 a first contact that is electrically connected to a gate runner; 
 a second contact that is separated from the first contact and electrically connected to a gate pad; and 
   at least one of the second trench structures comprises:
 a third contact that electrically connects only to either one of the gate runner or the gate pad. 
   
     
     
         17 . The semiconductor device according to  claim 15 , wherein
 the plurality of the second trench structures comprises:
 a first polysilicon that is electrically connected to a gate runner via a first contact and is electrically connected to a gate pad via a second contact; and 
 a second polysilicon that is electrically connected to the gate runner via a first contact and is not electrically connected to the gate pad via a second contact. 
   
     
     
         18 . The semiconductor device according to  claim 15 , wherein
 the polysilicon comprises:
 a first polysilicon that is electrically connected to a gate runner via a first contact and electrically connected to a gate pad via a second contact; and 
 a second polysilicon that is not electrically connected to the gate runner via a first contact and is electrically connected to the gate pad via a second contact. 
   
     
     
         19 . The semiconductor device according to  claim 15 , wherein
 each of at least two of the second trench structures comprise:
 a first contact that is electrically connected to a gate runner; and 
 a second contact that is separated from the first contact and electrically connected to a gate pad, and 
   the polysilicon comprises:
 a first polysilicon comprising at least a second trench structure of the plurality of second trench structures, the first polysilicon is electrically connected to the gate runner via a first contact and is electrically connected to the gate pad via a second contact; and 
 a second polysilicon comprising at least a second trench structure of the plurality of second trench structures, the second polysilicon is electrically connected to the gate runner via a first contact and is not electrically connected to the gate pad via a second contact. 
   
     
     
         20 . The semiconductor device according to  claim 15 , wherein
 each of at least two of the second trench structures comprises:
 a first contact that is electrically connected to a gate runner; and 
 a second contact that is separated from the first contact and electrically connected to a gate pad, and 
   the plurality of the second trench structures comprises:
 a first polysilicon comprising at least a second trench structure of the plurality of second trench structures, the first polysilicon is electrically connected to a gate runner via a first contact and is electrically connected to a gate pad via a second contact; and 
 a second polysilicon comprising at least a second trench structure of the plurality of second trench structures, the second polysilicon is not electrically connected to the gate runner via a first contact and is electrically connected to the gate pad via a second contact.