Source/Drain Structure of Semiconductor Device and Method of Forming Same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

1 . (canceled) 
     
     
         2 . A device comprising:
 a semiconductor fin extending from a substrate;   a gate stack extending along sidewalls and a top surface of the semiconductor fin; and   a source/drain region extending into the semiconductor fin adjacent to the gate stack, the source/drain region comprising:
 a first region in an interior of the source/drain region, the first region having a first dopant concentration; 
 a second region surrounding the first region, the second region having a second dopant concentration less than the first dopant concentration; and 
 a third region surrounding the second region, the third region having a third dopant concentration less than the second dopant concentration. 
   
     
     
         3 . The device of  claim 2 , wherein dopants of the source/drain region comprise arsenic (As), phosphorus (P), or antimony (Sb). 
     
     
         4 . The device of  claim 2 , wherein the source/drain region further comprises a fourth region surrounding the third region, the fourth region having a fourth dopant concentration less than the third dopant concentration. 
     
     
         5 . The device of  claim 2 , wherein the source/drain region further comprises:
 an epitaxial semiconductor material extending into the semiconductor fin to a first depth; and   a doped region of the semiconductor fin, the doped region of the semiconductor fin being disposed at a first interface between the epitaxial semiconductor material and the of the semiconductor fin.   
     
     
         6 . The device of  claim 5 , wherein the doped region of the semiconductor fin extends along the first interface to the first depth. 
     
     
         7 . The device of  claim 6 , further comprising a pn junction at a second interface between the doped region of the semiconductor fin and a channel region of the semiconductor fin. 
     
     
         8 . The device of  claim 5 , wherein a depth of the doped region is about equal to a depth of the epitaxial semiconductor material. 
     
     
         9 . A device comprising:
 a semiconductor fin protruding from a substrate;   a gate stack over the semiconductor fin;   a source/drain region in the semiconductor fin, wherein the source/drain region comprises:
 an epitaxial semiconductor material in the semiconductor fin; and 
 a doped region in the semiconductor fin along an interface between the epitaxial semiconductor material and the semiconductor fin, wherein the epitaxial semiconductor material and the doped region extend into the semiconductor fin to a same depth. 
   
     
     
         10 . The device of  claim 9 , wherein the doped region comprises a first n-type dopant and a second n-type dopant different than the first n-type dopant. 
     
     
         11 . The device of  claim 10 , wherein the first n-type dopant is arsenic. 
     
     
         12 . The device of  claim 11 , wherein the second n-type dopant is phosphorous. 
     
     
         13 . The device of  claim 9 , wherein a dopant concentration of the doped region is in a range of 1×10 18  cm −3  to 1×10 19  cm −3 . 
     
     
         14 . The device of  claim 9 , wherein the source/drain region comprises:
 a first region in an interior of the source/drain region, the first region having a first dopant concentration;   a second region surrounding the first region, the second region having a second dopant concentration less than the first dopant concentration; and   a third region surrounding the second region, the third region having a third dopant concentration less than the second dopant concentration.   
     
     
         15 . The device of  claim 14 , wherein the source/drain region further comprises a fourth region surrounding the third region, the fourth region having a fourth dopant concentration less than the third dopant concentration. 
     
     
         16 . A device comprising:
 a semiconductor fin extending from a substrate;   a gate stack extending along sidewalls and a top surface of the semiconductor fin;   gate spacers along sidewalls of the gate stack; and   a source/drain region extending into the semiconductor fin adjacent to the gate stack, the source/drain region comprising:
 an epitaxial semiconductor material; 
 a first region in an interior of the source/drain region, the first region having a first dopant concentration; 
 a second region surrounding the first region, the second region having a second dopant concentration less than the first dopant concentration; 
 a third region surrounding the second region, the third region having a third dopant concentration less than the second dopant concentration; and 
 a doped region in the semiconductor fin along an interface between the epitaxial semiconductor material and the semiconductor fin. 
   
     
     
         17 . The device of  claim 16 , wherein the epitaxial semiconductor material and the doped region extend into the semiconductor fin to a substantially same depth. 
     
     
         18 . The device of  claim 16 , wherein the doped region comprises a first dopant and a second dopant different from the first dopant. 
     
     
         19 . The device of  claim 18 , wherein the doped region comprises a third dopant different from the first dopant and the second dopant. 
     
     
         20 . The device of  claim 16 , wherein the source/drain region is an n-type source/drain region. 
     
     
         21 . The device of  claim 16 , wherein the doped region extends under the gate spacers.