Three-Dimensional Vertical Interconnect Architecture and Methods For Forming

Abstract

In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing.

1 . A method for forming a multiple die stack, comprising:
 forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer, each first circuit die has a power and circuit layer underlying a power and signal layer;   forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer, each interposer die has a power and signal layer underlying a power via and signal via layer; and   hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies, wherein the interposer wafer provides structural support of the first bonded wafer during subsequent processing.   
     
     
         2 . The method of  claim 1 , further comprising:
 flipping the first bonded wafer to expose the first circuit support layer of the first circuit wafer; and   performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer to remove the first circuit support layer to expose a plurality of power vias in the power and circuit layer of the first circuit wafer.   
     
     
         3 . The method of  claim 2 , further comprising:
 forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts, wherein the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer.   
     
     
         4 . The method of  claim 3 , further comprising:
 flipping the second bonded wafer to expose the top surface of the interposer wafer; and   performing a second CMP process or a second etching process on the interposer support layer to expose contact points of the power via and signal via layer of the interposer wafer.   
     
     
         5 . The method of  claim 4 , further comprising:
 reducing the interposer wafer to a total thickness of approximately 100 microns to approximately 200 microns when using vias with a critical dimension of approximately 5 microns to approximately 20 microns.   
     
     
         6 . The method of  claim 4 , further comprising:
 reducing the interposer wafer to a total thickness of approximately 5 microns to approximately 10 microns when using vias with a critical dimension of approximately 2 microns to approximately 4 microns.   
     
     
         7 . The method of  claim 4 , further comprising:
 forming a second circuit wafer with multiple second circuit dies, each second circuit die having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies of the interposer wafer.   
     
     
         8 . The method of  claim 7 , further comprising:
 hybrid bonding the bottom surface of the second circuit wafer to the top surface of the interposer wafer to form a third bonded wafer from the second bonded wafer to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer; and   dicing the third bonded wafer to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer, one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability.   
     
     
         9 . The method of  claim 8 , further comprising:
 forming a heatsink in contact with the second circuit die to remove heat from underlying circuits.   
     
     
         10 . The method of  claim 8 , further comprising:
 forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer; and   electrically connecting the PDN layer to the substrate.   
     
     
         11 . The method of  claim 7 , further comprising:
 dicing the second bonded wafer after performing the second CMP process or the second etching process to form partial vertical die stacks that are electrically connected from the second bonded wafer;   dicing the second circuit wafer to form second circuit dies; and   hybrid bonding one of the second circuit dies to one of the partial vertical die stacks to form a complete vertical die stack with backside power capability.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming a heatsink in contact with the second circuit die to remove heat from underlying circuits.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer; and   electrically connecting the PDN layer to the substrate.   
     
     
         14 . A method for forming a multiple die stack, comprising:
 forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer, each first circuit die has a power and circuit layer underlying a power and signal layer;   forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer, each interposer die has a power and signal layer underlying a power via and signal via layer;   hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies, wherein the interposer wafer provides structural support of the first bonded wafer during subsequent processing;   flipping the first bonded wafer to expose the first circuit support layer of the first circuit wafer;   performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer to remove the first circuit support layer to expose a plurality of power vias in the power and circuit layer of the first circuit wafer;   forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts, wherein the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer;   flipping the second bonded wafer to expose the top surface of the interposer wafer;   performing a second CMP process or a second etching process on the interposer support layer to expose contact points of the power via and signal via layer of the interposer wafer such that a thickness of the interposer wafer is approximately 100 microns to approximately 200 microns;   forming a second circuit wafer with multiple second circuit dies, each second circuit die having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies of the interposer wafer;   hybrid bonding the bottom surface of the second circuit wafer to the top surface of the interposer wafer to form a third bonded wafer from the second bonded wafer to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer; and   dicing the third bonded wafer to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer, one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability.   
     
     
         15 . The method of  claim 14 , further comprising:
 forming a heatsink in contact with the second circuit die to remove heat from underlying circuits.   
     
     
         16 . The method of  claim 14 , further comprising:
 forming at least one heat sink for an external power contact of the PDN layer in a substrate with contacts for electrically connecting with the PDN layer; and   electrically connecting the PDN layer to the substrate.   
     
     
         17 . A die stack with a vertical architecture comprising:
 a power delivery network (PDN) layer with a first backside power path and a first circuit power path;   a first circuit die with a first circuit, a second circuit power path electrically connected to the first circuit and the first circuit power path of the PDN layer, a second backside power path electrically connected to the first backside power path of the PDN layer, and a first signal path electrically connected to the first circuit;   an interposer die with a third backside power path electrically connected to the second backside power path of the first circuit die and a second signal path electrically connected to the first signal path of the first circuit die; and   a second circuit die with a power contact electrically connected to the third backside power path of the interposer die and a signal contact electrically connected to the second signal path of the interposer die.   
     
     
         18 . The die stack of  claim 17 , wherein the interposer die further includes a signal altering element interposed in the second signal path that electrically alters signal characteristics of signals traveling on the second signal path prior to reaching the second circuit die. 
     
     
         19 . The die stack of  claim 17 , wherein the first circuit die includes a plurality of first circuits and a plurality of first signal paths and a plurality of second circuit power paths and wherein the PDN layer includes a plurality of first circuit power paths that are electrically connected to the plurality of second circuit power paths in the first circuit die. 
     
     
         20 . The die stack of  claim 17 , further comprising:
 a heatsink in thermal contact with a top surface of the second circuit die.