Semiconductor device package interconnect and manufacturing method thereof

Abstract

A semiconductor device package, and method of manufacture is provided. The device includes a die, a substrate, a first connection area and a second connection area, the first connection area providing an electrical connection to the die, the second connection area providing an electrical connection to a substrate bond pad, and the first and connection area facing in the same direction. A non-conductive material is applied and cured between an edge of the first connection area and an edge of the second connection area and along a side of the die, and a conductive material is applied and cured between the first connection area and the second connection area and along a surface of the cured non-conductive material.

1 . A method of manufacturing a semiconductor device package comprising a die, a substrate, a first connection area and a second connection area,
 wherein the first connection area provides an electrical connection to the die,   wherein the second connection area provides an electrical connection to one of a substrate bond pad, a leadframe and a clip frame provided on the substrate,   wherein the first connection area and the second connection area are facing in the same direction,   wherein the method comprises the steps of:   applying a non-conductive material between an edge of the first connection area and an edge of the second connection area and along a side of the die, and curing the non-conductive material, thereby forming a first body of non-conductive material; and   applying one or more of a conductive material between the first connection area and the second connection area and along a surface of the first body of non-conductive material, and curing the conductive material, thereby forming a second body of conductive material.   
     
     
         2 . The method according to  claim 1 , further comprising repeating the step of applying the non-conductive material before applying the conductive material to enlarge the first body of non-conductive material. 
     
     
         3 . The method according to  claim 1 , wherein the step of curing of the non-conductive material is selected from the group consisting of: a box oven curing, and an ultra-violet (UV) curing. 
     
     
         4 . The method according to  claim 1 , wherein the step curing of the conductive material is selected from the group consisting of: a box oven curing, and sintering. 
     
     
         5 . The method according to  claim 1 , further comprising the step of applying a seed layer on the surface of the first body of non-conductive material before applying the conductive material. 
     
     
         6 . The method according to  claim 1 , wherein the method does not perform an etching or material removing of superfluous material from the first body of non-conductive material. 
     
     
         7 . The method according to  claim 1 , wherein the first connection area is an area on the die. 
     
     
         8 . The method according to  claim 7 , wherein the die is provided face down on the substrate. 
     
     
         9 . The method according to  claim 1 , wherein the first connection area is an area on a bond pad provided on the die. 
     
     
         10 . The method according to  claim 9 , wherein the die is provided face up on the substrate. 
     
     
         11 . A semiconductor device package manufactured using the method according to  claim 1 . 
     
     
         12 . The method according to  claim 2 , wherein the step of curing of the non-conductive material is selected from the group consisting of: a box oven curing, and an ultra-violet (UV), curing. 
     
     
         13 . The method according to  claim 2 , wherein the step curing of the conductive material is selected from the group consisting of: a box oven curing, and sintering. 
     
     
         14 . The method according to  claim 2 , further comprising the step of applying a seed layer on the surface of the first body of non-conductive material before applying the conductive material. 
     
     
         15 . The method according to  claim 2 , wherein the method does not perform an etching or material removing of superfluous material from the first body of non-conductive material. 
     
     
         16 . The semiconductor device package according to  claim 11 , wherein the device is one device selected from the group consisting of: a small outline diode (SOD), a clip bonded flat power package (CFP), a discrete package (Dpak), a dual discrete package (D 2 pak), a fan out panel level package (FOPLP), a loss-free package (LFPAK), and a copper clip package (CCPAK). 
     
     
         17 . The semiconductor device package according to  claim 11 , further comprising a high-power transistor. 
     
     
         18 . The semiconductor device package according to  claim 17 , further comprising a power metal-oxide-semiconductor field-effect transistor (power MOSFET). 
     
     
         19 . The semiconductor device package according to  claim 17 , further comprising an integrated circuit (IC).