Semiconductor interconnect structure with bottom self-aligned via landing

Abstract

A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor structure, comprising:
 forming a recess in a metal layer adjacent a dielectric layer;   forming an etch stop layer over the metal layer, within the recess, and over the dielectric layer;   removing a portion of the etch stop layer formed within the recess; and   forming a conductive via within the recess.   
     
     
         2 . The method of  claim 1 , wherein the dielectric layer comprises a first dielectric layer, the method further comprising:
 forming a second dielectric layer over the etch stop layer before removing the portion of the etch stop layer; and   removing a portion of the second dielectric layer before removing the portion of the etch stop layer.   
     
     
         3 . The method of  claim 2 , wherein removing the portion of the second dielectric layer comprises removing the portion of the second dielectric layer using a dual damascene process. 
     
     
         4 . The method of  claim 1 , wherein forming the etch stop layer comprises forming a layer of aluminum oxide over the metal layer, within the recess, and over the dielectric layer. 
     
     
         5 . The method of  claim 1 , wherein removing the portion of the etch stop layer comprises removing the portion of the etch stop layer using a wet etching process. 
     
     
         6 . The method of  claim 1 , wherein the metal layer comprises a first metal layer, the method further comprising forming a second metal layer adjacent the conductive via. 
     
     
         7 . The method of  claim 1 , further comprising planarizing a top surface of the metal layer before forming the recess in the metal layer. 
     
     
         8 . A method of fabricating a semiconductor structure, comprising:
 forming a first metal layer adjacent to a first dielectric layer;   recessing the first metal layer to form a first trench;   forming an etch stop layer over the first trench and the first dielectric layer;   forming a second dielectric layer over the etch stop layer to fill the first trench;   patterning the second dielectric layer to form a second trench, thereby exposing a portion of the etch stop layer;   removing the exposed portion of the etch stop layer to expose the first metal layer in the first trench; and   forming a second metal layer over the exposed first metal layer to form a via electrically coupled to the first metal layer.   
     
     
         9 . The method of  claim 8 , wherein forming the first metal layer includes:
 patterning the first dielectric layer to form a third trench,   forming the first metal layer over the patterned first dielectric layer, thereby filling the third trench, and   planarizing the first metal layer such that the first metal layer is planar with and adjacent to the first dielectric layer.   
     
     
         10 . The method of  claim 8 , further comprising providing a contact feature electrically coupled to a bottom surface of the first metal layer. 
     
     
         11 . The method of  claim 8 , wherein forming the etch stop layer includes conformally depositing an aluminum oxide layer. 
     
     
         12 . The method of  claim 11 , wherein removing the exposed portion of the etch stop layer includes performing a wet etching process. 
     
     
         13 . The method of  claim 8 , wherein recessing the first metal layer includes performing both a wet etching process and a dry etching process. 
     
     
         14 . The method of  claim 8 , wherein removing the exposed portion of the etch stop layer exposes a top surface of the first dielectric layer such that the second metal layer directly contacts the top surface of the first dielectric layer. 
     
     
         15 . The method of  claim 8 , wherein forming the second metal layer fills the first trench such that a bottom portion of the via directly contacts a sidewall of the first dielectric layer. 
     
     
         16 . A method of fabricating a semiconductor structure, comprising:
 forming a first metal layer adjacent to a first dielectric layer, the first metal layer having a top surface below a top surface of the first dielectric layer;   depositing an etch stop layer over the first metal layer and the first dielectric layer;   forming a second dielectric layer over the etch stop layer;   patterning the second dielectric layer to form a trench, the trench exposing sidewalls of the etch stop layer;   removing the exposed portion of the etch stop layer to expose the first metal layer; and   forming a second metal layer over the exposed first metal layer to form a via electrically coupled to the first metal layer.   
     
     
         17 . The method of  claim 16 , forming the first metal layer includes:
 patterning the first dielectric layer to form a second trench,   forming the first metal layer over the patterned first dielectric layer, thereby filling the second trench,   planarizing the first metal layer such that the first metal layer is planar with and adjacent to the first dielectric layer, and   recessing the planarized first metal layer.   
     
     
         18 . The method of  claim 16 , wherein removing the exposed portion of the etch stop layer exposes the top surface of the first dielectric layer. 
     
     
         19 . The method of  claim 16 , further comprising providing a contact feature electrically coupled to a bottom surface of the first metal layer, the contact feature including a gate contact, a source contact, or a drain contact. 
     
     
         20 . The method of  claim 16 , wherein the etch stop layer and the second dielectric layer have different compositions, and wherein the etch stop layer includes aluminum oxide.