Integrated circuit structure and method for fabricating the same

Abstract

A method for fabricating an integrated circuit structure is provided. The method includes forming a gate structure over a semiconductor substrate; forming a source/drain epitaxial structure adjacent a side of the gate structure; forming a first isolation structure in the gate structure, wherein the first isolation structure spaces apart a first portion of the gate structure from a second portion of the gate structure; forming a front-side metallization layer over a frontside of the semiconductor substrate, wherein the front-side metallization layer comprises a front-side metal feature overlapping the first isolation structure; depositing a dielectric layer over a backside of the semiconductor substrate; forming a conductive via in the dielectric layer and the first isolation structure, wherein the conductive via is in contact with a backside of the front-side metal feature.

What is claimed is: 
     
         1 . A method, comprising:
 forming a gate structure over a semiconductor substrate;   forming a source/drain epitaxial structure adjacent a side of the gate structure;   forming a first isolation structure in the gate structure, wherein the first isolation structure spaces apart a first portion of the gate structure from a second portion of the gate structure from a top view;   forming a front-side metallization layer over a frontside of the first isolation structure, wherein the front-side metallization layer comprises a front-side metal feature overlapping the first isolation structure;   depositing a dielectric layer over a backside of the first isolation structure; and   forming a conductive via in the dielectric layer and the first isolation structure, wherein the conductive via is in contact with the front-side metal feature.   
     
     
         2 . The method of  claim 1 , wherein forming the conductive via comprises:
 etching an opening in the dielectric layer, wherein the opening overlaps the first isolation structure;   deepening the opening such that the opening extends through the first isolation structure and exposes the front-side metal feature; and   depositing a conductive material into the deepened opening.   
     
     
         3 . The method of  claim 1 , further comprising:
 forming a contact plug on a backside of the source/drain epitaxial structure; and   forming a conductive line in the dielectric layer, wherein the conductive line is in contact with a backside of the contact plug.   
     
     
         4 . The method of  claim 3 , wherein a portion of the conductive via is at a same level height as the conductive line. 
     
     
         5 . The method of  claim 3 , wherein forming the conductive via and forming the conductive line comprises:
 etching a first opening in the dielectric layer and the first isolation structure;   etching a second opening in the dielectric layer and exposing the backside of the contact plug, wherein etching the second opening is performed such that the first opening is deepened to expose the front-side metal feature; and   depositing a conductive material into the first opening and the second opening.   
     
     
         6 . The method of  claim 1 , wherein a height of the conductive via is greater than a height of the gate structure. 
     
     
         7 . The method of  claim 1 , further comprising:
 forming a second isolation structure in the gate structure, wherein the second isolation structure spaces apart the second portion of the gate structure from a third portion of the gate structure, and forming the conductive via is performed such that the second isolation structure is free of a material of the conductive via.   
     
     
         8 . The method of  claim 7 , wherein a length of the second isolation structure along a direction perpendicular to a lengthwise direction of the gate structure is greater than a length of the first isolation structure along the direction from a top view. 
     
     
         9 . The method of  claim 7 , wherein a width of the second isolation structure along a lengthwise direction of the gate structure is less than a width of the first isolation structure along the lengthwise direction of the gate structure from a top view. 
     
     
         10 . The method of  claim 1 , wherein a first portion of the conductive via in the dielectric layer is formed of a same material composition as a second portion of the conductive via in the first isolation structure. 
     
     
         11 . A method, comprising:
 forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a sacrificial layer and a channel layer over the sacrificial layer;   patterning the epitaxial stack into a fin;   forming a dummy gate structure over the fin;   replacing the dummy gate structure and the sacrificial layer with a metal gate structure surrounding the channel layer;   forming an isolation structure in the metal gate structure, wherein the isolation structure spaces apart a first portion of the metal gate structure from a second portion of the metal gate structure from a top view; and   forming a conductive via in the isolation structure, wherein a height of the conductive via is greater than a height of the metal gate structure.   
     
     
         12 . The method of  claim 11 , further comprising:
 removing a portion of the semiconductor substrate to expose a backside of the isolation structure prior to forming the conductive via.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming shallow trench isolation (STI) structures around the fin, wherein forming the isolation structure is performed such that the isolation structure extends through the STI structures.   
     
     
         14 . The method of  claim 11 , wherein the first portion of the metal gate structure comprises an n-type work function metal layer, and the second portion of the metal gate structure comprises a p-type work function metal layer. 
     
     
         15 . An integrated circuit (IC) structure, comprising:
 a transistor comprising a channel layer, a gate structure surrounding the channel layer, and a source/drain epitaxial structure adjacent a side of the gate structure;   a first isolation structure in the gate structure, wherein the first isolation structure spaces apart a first portion of the gate structure from a second portion of the gate structure from a top view;   a front-side metallization layer over a frontside of the first isolation structure, wherein the front-side metallization layer comprises a front-side metal feature overlapping the first isolation structure;   a back-side metallization layer over a backside of the first isolation structure; and   a conductive via extending from the back-side metallization layer to the front-side metal feature through the first isolation structure.   
     
     
         16 . The IC structure of  claim 15 , wherein the conductive via is spaced apart from the gate structure by the first isolation structure. 
     
     
         17 . The IC structure of  claim 15 , wherein the back-side metallization layer comprises a dielectric layer and a metal line in the dielectric layer, wherein a portion of the conductive via is in the dielectric layer and at a same level height as the metal line. 
     
     
         18 . The IC structure of  claim 15 , wherein the conductive via tapers toward the front-side metallization layer. 
     
     
         19 . The IC structure of  claim 15 , wherein a height of the conductive via is greater than a height of the gate structure. 
     
     
         20 . The IC structure of  claim 15 , further comprises:
 a second isolation structure in the gate structure, wherein the second isolation structure spaces apart the second portion of the gate structure from a third portion of the gate structure, and the second isolation structure is free of a material of the conductive via.