Hybrid erase for data retention threshold voltage margin improvement

Abstract

A storage device is disclosed. The storage device is configured to perform a hybrid erase scheme comprising: performing an erase operation including simultaneously erasing memory cells associated with a block; and performing a stripe erase operation including simultaneously erasing memory cells associated with every other wordline of the block and then simultaneously erasing memory cells associated with remaining wordlines of the block.

What is claimed is: 
     
         1 . A storage device, comprising:
 a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and   a controller, coupled to the non-volatile memory, configured to:
 perform an erase operation including simultaneously erasing memory cells associated with a block; and 
 perform a stripe erase operation including simultaneously erasing memory cells associated with every other wordline of the block and then simultaneously erasing memory cells associated with remaining wordlines of the block. 
   
     
     
         2 . The storage device as set forth in  claim 1 , wherein the controller is further configured to:
 perform a verify operation on the memory cells associated with the block after applying a first erase pulse of the erase operation; and   in response to determining that the memory cells have completed erase, perform the stripe erase operation.   
     
     
         3 . The storage device as set forth in  claim 2 , wherein the controller is further configured to:
 in response to determining that the memory cells have not completed erase, apply a second erase pulse of the erase operation.   
     
     
         4 . The storage device as set forth in  claim 1 , wherein the controller is further configured to:
 perform a verify operation on the memory cells associated with the block after the stripe erase operation; and   in response to determining that the memory cells have not completed erase, perform another stripe erase operation.   
     
     
         5 . The storage device as set forth in  claim 4 , wherein performing the erase operation includes applying more than one erase pulse. 
     
     
         6 . The storage device as set forth in  claim 1 , wherein the stripe erase operation includes applying two erase pulses. 
     
     
         7 . The storage device as set forth in  claim 1 , wherein the stripe erase operation includes:
 during a first erase pulse, biasing the every other wordline of the block with a first bias and biasing the remaining wordlines of the block with a second bias, wherein the first bias is higher than the second bias; and   during a second erase pulse, biasing the every other wordline of the block with the second bias and biasing the remaining wordlines of the block with the first bias.   
     
     
         8 . A method of operating a memory apparatus including a plurality of memory cells, the method comprising the steps of:
 performing an erase operation including simultaneously erasing memory cells associated with a block; and   performing a stripe erase operation including simultaneously erasing memory cells associated with every other wordline of the block and then simultaneously erasing memory cells associated with remaining wordlines of the block.   
     
     
         9 . The method as set forth in  claim 8 , the method further including:
 performing a verify operation on the memory cells associated with the block after applying a first erase pulse of the erase operation; and   in response to determining that the memory cells have completed erase, performing the stripe erase operation.   
     
     
         10 . The method as set forth in  claim 9 , the method further including:
 in response to determining that the memory cells have not completed erase, applying a second erase pulse of the erase operation.   
     
     
         11 . The method as set forth in  claim 8 , the method further including:
 performing a verify operation on the memory cells associated with the block after the stripe erase operation; and   in response to determining that the memory cells have not completed erase, performing another stripe erase operation.   
     
     
         12 . The method as set forth in  claim 11 , wherein performing the erase operation includes applying more than one erase pulse. 
     
     
         13 . The method as set forth in  claim 8 , wherein performing the stripe erase operation includes applying two erase pulses. 
     
     
         14 . The method as set forth in  claim 8 , wherein performing the stripe erase operation includes:
 during a first erase pulse, biasing the every other wordline of the block with a first bias and biasing the remaining wordlines of the block with a second bias, wherein the first bias is higher than the second bias; and   during a second erase pulse, biasing the every other wordline of the block with the second bias and biasing the remaining wordlines of the block with the first bias.   
     
     
         15 . An apparatus comprising:
 a means for performing an erase operation including simultaneously erasing memory cells associated with a block; and   a means for performing a stripe erase operation including simultaneously erasing memory cells associated with every other wordline of the block and then simultaneously erasing memory cells associated with remaining wordlines of the block.   
     
     
         16 . The apparatus as set forth in  claim 15 , the apparatus further comprising:
 a means for performing a verify operation on the memory cells associated with the block after applying a first erase pulse of the erase operation; and   a means for performing the stripe erase operation in response to determining that the memory cells have completed erase.   
     
     
         17 . The apparatus as set forth in  claim 16 , the apparatus further comprising:
 a means for applying a second erase pulse of the erase operation in response to determining that the memory cells have not completed erase.   
     
     
         18 . The method as set forth in  claim 8 , the apparatus further including:
 a means for performing a verify operation on the memory cells associated with the block after the stripe erase operation; and   a means for performing another stripe erase operation in response to determining that the memory cells have not completed erase.   
     
     
         19 . The apparatus as set forth in  claim 18 , the apparatus further including:
 a means for applying more than one erase pulse when performing the erase operation.   
     
     
         20 . The apparatus as set forth in  claim 15 , the apparatus further including:
 a means applying two erase pulses when performing the stripe erase operation.