Embedded memory device and operating method thereof

Abstract

An embedded memory device includes a plurality of first bit cells configured to store data and connected between a first bitline and a first complementary bitline, and at least one first cropping cell connected between the first bitline and the first complementary bitline. The at least one first cropping cell electrically connects a global bitline to the first bitline and electrically connects a complementary global bitline to the first complementary bitline in response to a first crop wordline signal. The global bitline and the complementary global bitline are implemented as an upper metal member, and the first bitline and the first complementary bitline are implemented as a lower metal member disposed below the upper metal member.

1 . An embedded memory device comprising:
 a plurality of first bit cells configured to store data and connected between a first bitline and a first complementary bitline; and   at least one first cropping cell connected between the first bitline and the first complementary bitline, the at least one first cropping cell configured to electrically connect a global bitline to the first bitline and electrically connect a complementary global bitline to the first complementary bitline in response to a first crop wordline signal,   wherein the global bitline and the complementary global bitline are implemented as an upper metal member, and   wherein the first bitline and the first complementary bitline are implemented as a lower metal member disposed below the upper metal member.   
     
     
         2 . The embedded memory device of  claim 1 , wherein the plurality of first bit cells and the at least one first cropping cell are disposed inside a cell array of the embedded memory device. 
     
     
         3 . The embedded memory device of  claim 1 , wherein the at least one first cropping cell includes:
 an NMOS MUX configured to electrically connect the global bitline to the first bitline and electrically connect the complementary global bitline to the first complementary bitline based on the first crop wordline signal having a high-level.   
     
     
         4 . The embedded memory device of  claim 1 , wherein the at least one first cropping cell includes:
 a local pre-charger configured to pre-charge the first bitline and the first complementary bitline based on the first crop wordline signal having a low-level.   
     
     
         5 . The embedded memory device of  claim 1 , wherein the at least one first cropping cell includes:
 a cross-coupled PMOS switch configured to receive data from the global bitline and the complementary global bitline and maintain a voltage of the first bitline or the first complementary bitline based on the received data.   
     
     
         6 . The embedded memory device of  claim 1 , wherein, in a read operation of the embedded memory device, the embedded memory device is configured such that a charge of the global bitline is discharged to a selected bit cell through the first bitline. 
     
     
         7 . The embedded memory device of  claim 1 , wherein, in a write operation of the embedded memory device, the embedded memory device is configured such that the first complementary bitline is discharged to a ground voltage. 
     
     
         8 . The embedded memory device of  claim 1 , further comprising:
 a plurality of second bit cells connected between a second bitline and a second complementary bitline; and   at least one second cropping cell connected between the second bitline and the second complementary bitline,   wherein the at least one second cropping cell is configured to electrically connect the global bitline to the second bitline and electrically connect the complementary global bitline to the second complementary bitline in response to a second crop wordline signal.   
     
     
         9 . The embedded memory device of  claim 1 , wherein the at least one first cropping cell is implemented with the same poly, fin pitch, or pattern as a portion of the plurality of first bit cells. 
     
     
         10 . The embedded memory device of  claim 1 , wherein the at least one first cropping cell is implemented with the same metal routing pattern as a portion of adjacent bit cells among the plurality of first bit cells. 
     
     
         11 . An embedded memory device comprising:
 a plurality of subarrays sharing a plurality of global bitlines and a plurality of complementary global bitlines; and   a column peripheral circuit connected to the plurality of global bitlines and the plurality of complementary global bitlines,   wherein each of the plurality of subarrays includes:   a plurality of first cropping cells connected to a first crop wordline;   a plurality of second cropping cells connected to a second crop wordline; and   a plurality of bit cells configured to store data and connected to a plurality of bitlines and complementary bitlines and a plurality of wordlines,   wherein, in a write operation on bit cells connected to a wordline among the plurality of wordlines, the embedded memory device is configured such that each of the plurality of first cropping cells and the plurality of second cropping cells electrically connects bitlines to global bitlines corresponding to selected bit cells and electrically connects complementary bitlines to complementary global bitlines corresponding to the selected bit cells,   wherein the plurality of global bitlines and the complementary global bitlines are implemented as an upper metal member, and   wherein the plurality of bitlines and the plurality of complementary bitlines are implemented as a lower metal member disposed below the upper metal member.   
     
     
         12 . The embedded memory device of  claim 11 , wherein each of the first cropping cells and the second cropping cells includes:
 an NMOS MUX configured to electrically connect a corresponding global bitline to a corresponding bitline and electrically connect a corresponding complementary global bitline to a corresponding complementary bitline based on signals of the first and second crop wordlines each having a high-level;   a local pre-charger configured to pre-charge the corresponding bitline and the corresponding complementary bitline based on the signals of the first and second crop wordlines each having a low-level; and   a cross-coupled PMOS switch configured to receive data from the corresponding global bitline and the corresponding complementary global bitline and maintain a voltage of the corresponding bitline or the corresponding complementary bitline based on the received data.   
     
     
         13 . The embedded memory device of  claim 11 , further comprising:
 a wordline decoder configured to select one of the plurality of wordlines in response to an address; and   a crop wordline decoder configured to activate the first crop wordline and the second crop wordline in response to a clock.   
     
     
         14 . The embedded memory device of  claim 11 , wherein each of the plurality of first cropping cells and the plurality of second cropping cells is implemented with the same poly, fin pitch, or pattern as a portion of the plurality of bit cells, and implemented with the same metal routing pattern as a portion of adjacent bit cells among the plurality of bit cells. 
     
     
         15 . The embedded memory device of  claim 11 , wherein:
 in a read operation of the embedded memory device, the embedded memory device is configured such that a charge of a corresponding global bitline is discharged to a selected bit cell through a corresponding bitline, and   in the write operation, the embedded memory device is configured such that a complementary bitline corresponding to the selected bit cell is discharged to a ground voltage.   
     
     
         16 . An operating method of an embedded memory device including a plurality of bit cells connected to a local bitline, the operating method comprising:
 electrically connecting the local bitline to a global bitline using at least one cropping cell; and   performing a write operation on a selected bit cell connected to the local bitline,   wherein the global bitline is implemented as an upper metal member, and   wherein the local bitline is implemented as a lower metal member disposed below the upper metal member.   
     
     
         17 . The operating method of  claim 16 , wherein the performing of the write operation on the selected bit cell includes:
 selecting a wordline connected to the selected bit cell among a plurality of wordlines by applying a high-level.   
     
     
         18 . The operating method of  claim 16 , wherein the performing of the write operation on the selected bit cell includes setting a clock signal to a high-level during the write operation, and
 wherein the electrically connecting of the local bitline and the global bitline includes providing a crop wordline signal to the at least one cropping cell by setting the clock signal.   
     
     
         19 . The operating method of  claim 18 , wherein the electrically connecting of the local bitline and the global bitline is performed when the crop wordline signal is at a high-level. 
     
     
         20 . The operating method of  claim 18 , further comprising:
 pre-charging the local bitline when the crop wordline signal is at a low-level.   
     
     
         21 - 25 . (canceled)