Method to reset configurable units in a reconfigurable processor

Abstract

Disclosed is a method for resetting configurable units in a reconfigurable processor with an array of configurable units and a force-quit controller on an integrated circuit substrate. The array includes multiple sub-arrays of configurable units. The method involves receiving a force-quit command at the force-quit controller and generating force-quit control signals to reset configurable units in a specific sub-array of the plurality of sub-arrays. The specific sub-array contains the force-quit controller. This method enhances the efficiency and reliability of reconfigurable processors by enabling targeted and controlled resets of configurable units within the reconfigurable processor architecture.

What is claimed is: 
     
         1 . A method to reset configurable units in a reconfigurable processor having an array of configurable units and a force-quit controller on an integrated circuit substrate, the array including a plurality of sub-arrays of configurable units, the method comprising:
 receiving a force-quit command at the force-quit controller, and   generating force-quit control signals that reset configurable units in a particular sub-array of the plurality of sub-arrays of configurable units;   wherein the particular sub-array includes the force-quit controller.   
     
     
         2 . The method of  claim 1 , further comprising sending the force-quit command to the force-quit controller from an interface agent included in the reconfigurable processor, wherein the interface agent communicates data between the array and an interface bus over a top level network, and wherein the interface bus is connected to a host processor via an interface link. 
     
     
         3 . The method of  claim 2 , further comprising completing, by the particular sub-array, outstanding transactions on the top level network in response to receiving the force-quit control signals from the force-quit controller. 
     
     
         4 . The method of  claim 2 , further comprising:
 receiving, at the interface agent from a runtime program running on a host processor, a force-quit message written to a register in an address space of the interface bus by a runtime program running on a host processor; and   sending the force-quit command to the force-quit controller in response to receiving the force-quit message.   
     
     
         5 . The method of  claim 4 , wherein the register is located in a configuration address space of the interface bus. 
     
     
         6 . The method of  claim 4 , further comprising:
 receiving a sequence of writes to the register; and   recognizing the sequence of writes to the register as the force-quit message.   
     
     
         7 . The method of  claim 6 , wherein the sequence of writes to the register includes:
 a first set of one or more writes to the register to represent a function header;   a second set of one or more writes to the register to represent a function select; and   a third set of one or more writes to the register to represent a sub-array-specific function argument.   
     
     
         8 . The method of  claim 7 , wherein the sub-array-specific function argument makes the force-quit message specific to the particular sub-array. 
     
     
         9 . The method of  claim 6 , further comprising sending the force-quit command as a strobe signal in response to recognizing the sequence of writes to the register as the force-quit message. 
     
     
         10 . The method of  claim 9 , further comprising sending the force-quit command from the interface agent to the force-quit controller via a global wire. 
     
     
         11 . The method of  claim 4 , wherein the force-quit message includes a mask having one bit respectively associated with each sub-array in the plurality of sub-arrays and each sub-array has a respective force-quit controller, the method further comprising:
 for each bit in the mask that is set, sending a respective force-quit command to the respective force-quit controller of the sub-array associated with the set bit.   
     
     
         12 . The method of  claim 1 , further comprising broadcasting the force-quit control signals from the force-quit controller to the configurable units in the particular sub-array over an array level network connected to the configurable units in the particular sub-array. 
     
     
         13 . The method of  claim 1 , further comprising resetting an internal state of the configurable units in the particular sub-array in response to receiving the force-quit control signals. 
     
     
         14 . The method of  claim 1 , further comprising emptying input buffers and output buffers of the configurable units in the particular sub-array in response to receiving the force-quit control signals. 
     
     
         15 . The method of  claim 1 , wherein the particular sub-array is unresponsive while executing a current program, and the force-quit control signals cause the configurable units in the particular sub-array to be available for execution of a next program. 
     
     
         16 . The method of  claim 1 , the particular sub-array of configurable units including a plurality of force-quit logic circuits associated with respective configurable units of the particular sub-array of configurable units and connected in an interconnect topology, the method further comprising:
 receiving a particular force-quit control signal of the force-quit control signals at a particular force-quit logic circuit of the plurality of force-quit logic circuits;   resetting the respective configurable unit associated with the particular force-quit logic circuit in response to the particular force-quit control signal;   generating a particular force-quit done signal to indicate completion of the reset of the respective configurable unit associated with the particular force-quit logic circuit,   receiving a preceding force-quit done signal is a preceding force-quit logic circuit on the interconnect topology; and   forwarding the particular force-quit done signal on the interconnect topology in response to receiving the preceding force-quit done signal.   
     
     
         17 . The method of  claim 16 , further comprising:
 broadcasting the force-quit control signals from the force-quit controller to the configurable units of the particular sub-array of configurable units; and   receiving a force-quit done signal from a last force-quit logic circuit on the interconnect topology.   
     
     
         18 . The method of  claim 16 , further comprising:
 transitioning the respective configurable unit associated with the particular force-quit logic circuit from a current state to a force-quit drain state in response to the particular force-quit control signal;   while in the force-quit drain state, de-asserting the particular force-quit done signal to the interconnect topology, and starting a force-quit drain counter;   upon expiration of the force-quit drain counter, transitioning the respective configurable unit associated with the particular force-quit logic circuit from the force-quit drain state to a force-quit done state; and   while in the force-quit done state, asserting the particular force-quit done signal to the interconnect topology in response to an input port from the interconnect topology being asserted.   
     
     
         19 . The method of  claim 16 , wherein the interconnect topology comprises a daisy chain. 
     
     
         20 . The method of  claim 16 , each configurable unit in the particular sub-array of configurable units having a FORCE_QUIT_DONE_IN input and a FORCE_QUIT_DONE_OUT output, the FORCE_QUIT_DONE_OUT output asserted only while both FORCE_QUIT_DONE_IN and a signal indicating that the respective configurable unit are asserted.