Field effect transistor with top-protected gate electrode and methods for forming the same

Abstract

A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.

What is claimed is: 
     
         1 . A semiconductor structure comprising a first field effect transistor, wherein the first field effect transistor comprises:
 a first source region and a first drain region embedded in a first portion of a semiconductor substrate;   a first gate dielectric overlying a first channel region located between the first source region and the first drain region;   a first gate electrode overlying the first gate dielectric;   a first dielectric gate liner laterally surrounding the first gate electrode;   a first inner gate spacer laterally surrounding the first dielectric gate liner;   a contoured gate capping dielectric comprising a vertically-extending portion that laterally surrounds the first inner gate spacer and a first horizontally-extending portion that overlies the first gate electrode; and   a first outer gate spacer laterally surrounding the contoured gate capping dielectric.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the contoured gate capping dielectric comprises a second horizontally-extending portion that is adjoined to a bottom region of the vertically-extending portion and underlies the first outer gate spacer. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the second horizontally-extending portion of the contoured gate dielectric contacts a topmost surface of the first source region and a topmost surface of the first drain region. 
     
     
         4 . The semiconductor structure of  claim 2 , wherein the first field effect transistor comprises:
 a first source extension region adjoined to the first source region; and   a first drain extension region adjoined to the first drain region,   wherein the first source extension region comprises a first topmost source extension surface segment that contacts a bottom surface of the first dielectric gate liner and a first recessed source extension surface segment that contacts a bottom surface of the second horizontally-extending portion of the contoured gate capping dielectric.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein the first source extension region comprises a first vertically-extending surface segment that connects the first topmost source extension surface segment and the first recessed source extension surface segment, and is in contact with a vertical surface segment of the second horizontally-extending portion of the contoured gate capping dielectric. 
     
     
         6 . The semiconductor structure of  claim 2 , wherein:
 the second horizontally-extending portion of the contoured gate capping dielectric has a first thickness; and   the first horizontally-extending portion of the contoured gate capping dielectric has a second thickness that is in a range from 40% to 90% of the first thickness.   
     
     
         7 . The semiconductor structure of  claim 6 , wherein a lateral thickness of the vertically-extending portion of the contoured gate capping dielectric is the first thickness. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein each surface segment of the first inner gate spacer is in contact with a respective surface segment of a combination of the first dielectric gate liner and the contoured capping gate dielectric. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein:
 the first dielectric gate liner comprises a first silicon oxide material;   the first inner gate spacer comprises a first silicon nitride material;   the contoured gate capping dielectric comprises a second silicon oxide material; and   the first outer gate spacer comprises a second silicon nitride material.   
     
     
         10 . The semiconductor structure of  claim 1 , further comprising a second field effect transistor that comprises:
 a second source region and a second drain region embedded in a second portion of the semiconductor substrate;   a second gate dielectric overlying a second channel region located between the second source region and the second drain region;   a second gate electrode overlying the second gate dielectric;   a second dielectric gate liner laterally surrounding the second gate electrode;   a second inner gate spacer laterally surrounding the second dielectric gate liner; and   a second outer gate spacer laterally surrounding the second inner gate spacer, wherein the second outer gate spacer is in direct contact with the second inner gate spacer or is spaced from the second inner gate spacer by a native oxide layer having a thickness less than 1 nm.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the vertically-extending portion of the contoured gate capping dielectric has a thickness in a range from 10 nm to 60 nm. 
     
     
         12 . A semiconductor structure comprising:
 a first field effect transistor; and   a second field effect transistor, wherein the first field effect transistor comprises:
 a first source region and a first drain region embedded in a first portion of a semiconductor substrate; 
 a first gate dielectric and a first gate electrode; 
 a first dielectric gate liner laterally surrounding the first gate electrode; 
 a first inner gate spacer laterally surrounding the first dielectric gate liner; 
 a contoured gate capping dielectric comprising a vertically-extending portion that laterally surrounds the first inner gate spacer and a first horizontally-extending portion that overlies the first gate electrode; and 
 a first outer gate spacer laterally surrounding the contoured gate capping dielectric, 
   and wherein the second field effect transistor comprises:
 a second source region and a second drain region embedded in a second portion of the semiconductor substrate; 
 a second gate dielectric and a second gate electrode; 
 a second dielectric gate liner laterally surrounding the second gate electrode and having a same material composition as the first dielectric gate liner; 
 a second inner gate spacer laterally surrounding the second dielectric gate liner and having a same material composition as the first inner gate spacer; and 
 a second outer gate spacer laterally surrounding the second inner gate spacer and having a same material composition as the first outer gate spacer, wherein the second outer gate spacer is in direct contact with the second inner gate spacer or is spaced from the second inner gate spacer by a native oxide layer having a thickness less than 1 nm. 
   
     
     
         13 . The semiconductor structure of  claim 12 , wherein the contoured gate capping dielectric comprises a second horizontally-extending portion that is adjoined to a bottom region of the vertically-extending portion and underlies the first outer gate spacer. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein:
 the second horizontally-extending portion of the contoured gate capping dielectric has a first thickness; and   the first horizontally-extending portion of the contoured gate capping dielectric has a second thickness that is in a range from 40% to 90% of the first thickness.   
     
     
         15 . The semiconductor structure of  claim 12 , further comprising a first gate contact via structure contacting a top surface of the second gate electrode, wherein all surface segments of the first gate electrode is in contact with a respective surface segment of a combination of the first gate dielectric, the first dielectric gate liner, and the first horizontally-extending portion of the contoured gate capping dielectric. 
     
     
         16 . A method of forming a semiconductor structure, the method comprising:
 forming a first gate dielectric and a first gate electrode over a first portion of a semiconductor substrate;   forming a combination of a first dielectric gate liner and a first inner gate spacer around the first gate electrode;   forming a combination of a contoured gate capping dielectric and a first outer gate spacer, wherein the contoured gate capping dielectric comprises a vertically-extending portion that laterally surrounds the first inner gate spacer and a first horizontally-extending portion that overlies the first gate electrode, and the first outer gate spacer laterally surrounds the contoured gate capping dielectric; and   forming a first source region and a first drain region in the first portion of the semiconductor substrate adjacent to the combination of the contoured gate capping dielectric and the first outer gate spacer.   
     
     
         17 . The method of  claim 16 , further comprising:
 forming a capping dielectric material layer over the combination of the first dielectric gate liner and the first inner gate spacer;   forming an outer spacer material layer over a first portion the capping dielectric material layer; and   anisotropically etching the outer spacer material layer and the first portion of the capping dielectric material layer, wherein the contoured gate capping dielectric comprises a patterned portion of the capping dielectric material layer, and the first outer gate spacer comprises a patterned portion of the outer spacer material layer.   
     
     
         18 . The method of  claim 17 , wherein:
 the contoured gate capping dielectric comprises a second horizontally-extending portion that underlies the first outer gate spacer and a third horizontally-extending portion that does not underlie the first outer gate spacer;   the first source region and the first drain region are formed by implantation of atoms of a dopant species through the third horizontally-extending portion of the contoured gate capping dielectric; and   the method comprises removing the third horizontally-extending portion of the contoured gate capping dielectric after formation of the source region and the drain region.   
     
     
         19 . The method of  claim 17 , further comprising:
 forming a second gate dielectric and a second gate electrode over a second portion of the semiconductor substrate;   forming a combination of a second dielectric gate liner and a second inner gate spacer around the second gate electrode;   removing a second portion of the capping dielectric material layer overlying the second portion of the semiconductor substrate without removing the first portion of the capping dielectric material layer.   
     
     
         20 . The method of  claim 16 , further comprising:
 conformally depositing a dielectric liner material layer and an inner spacer material layer over the first gate electrode; and   anisotropically etching the inner spacer material layer and the dielectric liner material layer, wherein the first dielectric gate liner comprises a remaining portion of the dielectric liner material layer, and the first inner gate spacer comprises a remaining portion of the inner spacer material layer.