Methods For Forming Source/Drain Features

Abstract

A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a plurality of nanostructures over a substrate;   a gate structure over and wrapping around the plurality of nanostructures;   a source/drain feature coupled to the plurality of nanostructures, wherein in a cross-sectional view cut through the source/drain feature without cutting through the gate structure, the source/drain feature comprises an upper portion and a lower portion under the upper portion, and the lower portion has a first sidewall and a second sidewall opposing the first sidewall, the first sidewall and the second sidewall are both substantially straight sidewalls;   a first dielectric liner disposed under the upper portion of the source/drain feature and covering the first sidewall of the lower portion source/drain feature; and   a second dielectric liner disposed under the upper portion of the source/drain feature covering the second sidewall of the lower portion source/drain feature.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising:
 an etch stop layer extending along the first dielectric liner, the second dielectric liner, and the upper portion of the source/drain feature.   
     
     
         3 . The semiconductor structure of  claim 1 , wherein a height of the first dielectric liner is equal to a height of the second dielectric liner. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein a width of the upper portion of the source/drain feature is non-uniform in the cross-sectional view. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the upper portion of the source/drain feature spans a first width in the cross-sectional view, and the lower portion of the source/drain feature spans a second width in the cross-sectional view, the second width is different than the first width. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein the second width is less than the first width. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising:
 an isolation feature over the substrate and under the source/drain feature,   wherein the first and second dielectric liners are disposed directly on the isolation feature.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the first and second dielectric liners comprise aluminum oxide, hafnium oxide, silicon oxycarbide, or silicon oxynitride. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising:
 inner spacer features providing isolation between the gate structure and the source/drain feature,   wherein the inner spacer features and the first and second dielectric liners have different compositions.   
     
     
         10 . A semiconductor structure, comprising:
 a source/drain feature over a portion of a substrate and having a lower portion and an upper portion, wherein the lower portion has a substantially straight sidewall;   a dielectric spacer extending along the lower portion of the source/drain feature;   a conformal dielectric layer extending over both the upper portion of the source/drain feature and the dielectric spacer,   wherein a composition of the dielectric spacer is different than a composition of the conformal dielectric layer.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the upper portion of the source/drain feature spans a first width, the lower portion of the source/drain feature spans a second width less than the first width. 
     
     
         12 . The semiconductor structure of  claim 10 , wherein the upper portion of the source/drain feature has a non-uniform width. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein the dielectric spacer comprises aluminum oxide, hafnium oxide, silicon oxycarbide, or silicon oxynitride. 
     
     
         14 . The semiconductor structure of  claim 10 ,
 wherein the source/drain feature is an N-type source/drain feature, the dielectric spacer is a first dielectric spacer, and the semiconductor structure further comprises a P-type source/drain feature and a second dielectric layer extending along a lower portion of the second source/drain feature,   wherein the first dielectric layer and the second dielectric layer have a same height.   
     
     
         15 . The semiconductor structure of  claim 10 , further comprising:
 a plurality of nanostructures over the substrate; and   a gate structure wrapping around each of plurality of nanostructures,   wherein the source/drain feature is coupled to the plurality of nanostructures and spaced apart from the gate structure by a plurality of inner spacer features.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the plurality of inner spacer features and the dielectric spacer have different compositions. 
     
     
         17 . A semiconductor structure, comprising:
 a substrate including a first mesa structure and a second mesa structure protruding from the substrate;   a first vertical stack of nanostructures disposed over the first mesa structure;   a first source/drain feature disposed over the first mesa structure and adjacent to the first vertical stack of nanostructures along a first direction;   a second vertical stack of nanostructures disposed over the second mesa structure;   a second source/drain feature disposed over the second mesa structure and adjacent to the second vertical stack of nanostructures along the first direction, the second source/drain feature being disposed adjacent to the first source/drain feature along a second direction perpendicular to the first direction;   a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures;   a second gate structure wrapping around each nanostructure of the second vertical stack of nanostructures;   a first spacer extending along a sidewall surface of a lower portion of the first source/drain feature; and   a second spacer extending along a sidewall surface of a lower portion of the second source/drain feature,   wherein the lower portion the first source/drain feature is spaced apart from the lower portion of the second source/drain feature by the first spacer, the second spacer, a contact etch stop layer, and a dielectric layer.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein a height of the first spacer is different than a height of the second spacer. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein a composition of the first spacer is different than a composition of the second spacer. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein the first spacer comprises aluminum oxide, silicon oxynitride, silicon oxycarbonitride, or hafnium oxide.