Semiconductor memory device and method for fabricating the same

Abstract

A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor memory device, comprising:
 forming a conductive line on a substrate that extends in a first direction;   forming a first interlayer insulating layer on the substrate, the first interlayer insulating layer exposing at least a portion of the conductive line and defining a channel trench extending in a second direction crossing the first direction;   forming a channel layer extending along a bottom surface of the channel trench and along a side surface of the channel trench;   forming a preliminary gate insulating layer on the channel layer, the preliminary gate insulating layer extending along the channel layer;   forming a preliminary gate electrode layer on the gate insulating layer, the preliminary gate electrode layer extending along the preliminary gate insulating layer; and   cutting the preliminary gate electrode layer to form a first gate electrode and a second gate electrode spaced apart from each other in the first direction,   wherein the forming of the channel layer comprises sequentially stacking a first oxide semiconductor layer and a second oxide semiconductor layer on the conductive line, and   the first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.   
     
     
         2 . The method of  claim 1 , wherein the forming of the preliminary gate insulating layer comprises sequentially stacking a first dielectric layer and a second dielectric layer on the channel layer, and
 the second dielectric layer has a higher dielectric constant than the first dielectric layer.   
     
     
         3 . The method of  claim 2 , wherein the first dielectric layer includes silicon oxide, and
 the second dielectric layer includes at least one of aluminum oxide or hafnium oxide.   
     
     
         4 . The method of  claim 1 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium (In). 
     
     
         5 . The method of  claim 4 , wherein the first oxide semiconductor layer includes at least one of spinel indium gallium zinc oxide (IGZO) or c-axis aligned crystalline IGZO (CAAC IGZO), and
 the second oxide semiconductor layer includes at least one of amorphous IGZO, amorphous indium tin oxide (ITO), or amorphous indium gallium tin oxide (IGTO).   
     
     
         6 . The method of  claim 1 , further comprising:
 forming, in the channel layer, a separation trench extending in the first direction to cut the channel layer.   
     
     
         7 . The method of  claim 1 , further comprising:
 forming, a first capacitor structure on the first interlayer insulating layer and connected to one end of the channel layer adjacent to the first gate electrode; and   forming a second capacitor structure on the first interlayer insulating layer and connected to the other end of the channel layer adjacent to the second gate electrode.   
     
     
         8 . The method of  claim 1 , further comprising:
 forming, a peripheral circuit element on the substrate and electrically connected to the conductive line; and   forming an inter-wire insulating layer on the substrate covering the peripheral circuit element,   wherein the first interlayer insulating layer is stacked on a top surface of the inter-wire insulating layer.   
     
     
         9 . The method of  claim 1 , further comprising:
 forming, a first landing pad on one end of the channel layer adjacent to the first gate electrode; and   forming, a second landing pad on the other end of the channel layer adjacent to the second gate electrode.   
     
     
         10 . The method of  claim 9 , wherein the first landing pad contacts at least a part of a side surface of the channel layer. 
     
     
         11 . A method for fabricating a semiconductor memory device, comprising:
 forming a conductive line on a substrate that extends in a first direction;   forming a first interlayer insulating layer on the substrate, the first interlayer insulating layer exposing at least a portion of the conductive line and defining a channel trench extending in a second direction crossing the first direction;   forming a channel layer extending along a bottom surface of the channel trench and along a side surface of the channel trench;   forming a preliminary gate insulating layer on the channel layer, the preliminary gate insulating layer extending along the channel layer;   forming a preliminary gate electrode layer on the gate insulating layer, the preliminary gate electrode layer extending along the preliminary gate insulating layer;   cutting the preliminary gate electrode layer to form a first gate electrode and a second gate electrode spaced apart from each other in the first direction;   forming, a first landing pad on one end of the channel layer adjacent to the first gate electrode; and   forming, a second landing pad on the other end of the channel layer adjacent to the second gate electrode,   wherein the forming of the channel layer comprises sequentially stacking a first oxide semiconductor layer and a second oxide semiconductor layer on the conductive line,   wherein the forming of the preliminary gate insulating layer comprises sequentially stacking a first dielectric layer and a second dielectric layer on the channel layer,   the first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer, and   the second dielectric layer has a higher dielectric constant than the first dielectric layer.   
     
     
         12 . The method of  claim 11 , wherein the first dielectric layer includes silicon oxide, and
 the second dielectric layer includes at least one of aluminum oxide or hafnium oxide.   
     
     
         13 . The method of  claim 11 , wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium (In). 
     
     
         14 . The method of  claim 13 , wherein the first oxide semiconductor layer includes at least one of spinel indium gallium zinc oxide (IGZO) or c-axis aligned crystalline IGZO (CAAC IGZO), and
 the second oxide semiconductor layer includes at least one of amorphous IGZO, amorphous indium tin oxide (ITO), or amorphous indium gallium tin oxide (IGTO).   
     
     
         15 . The method of  claim 11 , further comprising:
 forming, in the channel layer, a separation trench extending in the first direction to cut the channel layer.   
     
     
         16 . The method of  claim 11 , further comprising:
 forming, a first capacitor structure on the first interlayer insulating layer and connected to the first landing pad, and   forming a second capacitor structure on the first interlayer insulating layer and connected to the second lading pad.   
     
     
         17 . The method of  claim 11 , wherein the first landing pad contacts at least a part of a side surface of the channel layer. 
     
     
         18 . A method for fabricating a semiconductor memory device, comprising:
 forming, a peripheral circuit element and an inter-wire insulating layer covering the peripheral circuit element on a substrate;   forming a conductive line on the substrate that extends in a first direction;   forming a first interlayer insulating layer on the substrate, the first interlayer insulating layer exposing at least a portion of the conductive line and defining a channel trench extending in a second direction crossing the first direction;   forming a channel layer extending along a bottom surface of the channel trench and along a side surface of the channel trench;   forming a preliminary gate insulating layer on the channel layer, the preliminary gate insulating layer extending along the channel layer;   forming a preliminary gate electrode layer on the gate insulating layer, the preliminary gate electrode layer extending along the preliminary gate insulating layer;   cutting the preliminary gate electrode layer to form a first gate electrode and a second gate electrode spaced apart from each other in the first direction;   forming, a first landing pad on one end of the channel layer adjacent to the first gate electrode; and   forming, a second landing pad on the other end of the channel layer adjacent to the second gate electrode,   wherein the forming of the channel layer comprises sequentially stacking a first oxide semiconductor layer and a second oxide semiconductor layer on the conductive line,   wherein the forming of the preliminary gate insulating layer comprises sequentially stacking a first dielectric layer and a second dielectric layer on the channel layer,   the first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer, and   the second dielectric layer has a higher dielectric constant than the first dielectric layer.   
     
     
         19 . The method of  claim 18 , wherein the first oxide semiconductor layer includes at least one of spinel indium gallium zinc oxide (IGZO) or c-axis aligned crystalline IGZO (CAAC IGZO), and
 the second oxide semiconductor layer includes at least one of amorphous IGZO, amorphous indium tin oxide (ITO), or amorphous indium gallium tin oxide (IGTO).   
     
     
         20 . The method of  claim 18 , wherein the first landing pad contacts at least a part of a side surface of the channel layer.