Robust platform low power mode via embedded controller-based health policy to correct anomalous computer idle conditions

Abstract

Embodiments herein relate to a computing device in which an embedded controller (EC) detects an anomalous low power state. When a processor in a chip package enters a low power state such as a deep idle state, the EC obtains information to verify whether activity of the processor is consistent with the low power state. The EC can communicate with the chip package via a serial peripheral interface to obtain counter data indicating an idle state residency of subsystems of the chip package, along with internal temperature data. The EC can also access data from an external temperature sensor and a battery fuel gauge. The EC determines whether the counter data, temperature and battery discharge rate are inconsistent with the processor entering the low power state. If there is an inconsistency, the EC can shutdown or restart the computing device.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a chip package comprising a processor and one or more counters, wherein each counter of the one or more counters is to provide a count which represents an idle time of a respective subsystem of one or more subsystems;   an embedded controller (EC); and   a serial peripheral interface (SPI) bus coupled to the chip package and the embedded controller, wherein when the processor enters a low power state, the EC is to obtain the count from each counter of the one or more counters via the SPI bus, and determine whether activity of the processor is inconsistent with the low power state based on the count from each counter of the one or more counters.   
     
     
         2 . The apparatus of  claim 1 , wherein:
 the chip package is to transmit a C10 signal and an SLP_S0# signal to a voltage regulator;   
       the C10 signal indicates whether the processor is in the low power state;
 the SLP_S0# signal indicates whether a platform of the processor is in the low power state; and 
 the EC is to determine whether the activity of the processor is inconsistent with the low power state without accessing the C10 signal or the SLP_S0# signal. 
 
     
     
         3 . The apparatus of  claim 1 , wherein the one or more subsystems comprise at least one of a Serial Advanced Technology Attachment (SATA) interface, an audio controller, a hard drive controller, a Universal Serial Bus (USB) controller, or a Peripheral Component Interconnect (PCI) express interface. 
     
     
         4 . The apparatus of  claim 1 , wherein when the EC determines that the activity of the processor is inconsistent with the low power state, the EC is to initiate a fail safe mode for the apparatus. 
     
     
         5 . The apparatus of  claim 4 , wherein the fail safe mode comprises a suspend, shutdown or restart of the apparatus. 
     
     
         6 . The apparatus of  claim 1 , wherein the low power state comprises a deep idle state. 
     
     
         7 . The apparatus of  claim 1 , wherein when the processor enters the low power state, the EC is to obtain internal temperature data of the processor via the SPI bus and determine whether the activity of the processor is inconsistent with the low power state based on the internal temperature data. 
     
     
         8 . The apparatus of  claim 1 , wherein when the processor enters the low power state, the EC is to obtain external temperature data, external to the chip package, and determine whether the activity of the processor is inconsistent with the low power state based on the external temperature data. 
     
     
         9 . The apparatus of  claim 1 , wherein the processor is powered by a battery, and when the processor enters the low power state, the EC is to determine a discharge rate of the battery, and determine whether the activity of the processor is inconsistent with the low power state based on whether the discharge rate of the battery exceeds a threshold. 
     
     
         10 . The apparatus of  claim 1 , wherein when the processor enters the low power state, the EC receives a notification from a basic input output system (BIOS) of the processor and initiates the obtaining of the count from each counter of the one or more counters in response to the notification. 
     
     
         11 . An apparatus, comprising:
 a processor;   one or more counters, wherein each counter of the one or more counters is to provide a count which represents a portion of a time period in which a respective subsystem of one or more subsystems is idle; and   a pin coupled to a serial peripheral interface (SPI) bus to communicate with an embedded controller (EC), wherein the apparatus is to notify the EC via the SPI bus when the processor enters a low power state, and to transmit the count from each counter of the one or more counters to the EC via the SPI bus in response to a request from the EC via the SPI bus.   
     
     
         12 . The apparatus of  claim 11 , wherein the processor is on a system-on-a-chip (SoC), and the SoC is to notify the EC via the SPI bus when the processor enters the low power state, and to transmit the count from each counter of the one or more counters to the EC via the SPI bus in response to the request from the EC via the SPI bus. 
     
     
         13 . The apparatus of  claim 11 , further comprising another pin to transmit a signal to a voltage regulator when the processor enters the low power state, wherein the another pin is not coupled to the EC. 
     
     
         14 . The apparatus of  claim 11 , further comprising other pins to transmit a C10 signal and an SLP_S0# signal to a voltage regulator, wherein the C10 signal indicates whether the processor is in the low power state, the SLP_S0# signal indicates whether a platform of the processor is in the low power state, and the other pins are not coupled to the EC. 
     
     
         15 . The apparatus of  claim 11 , further comprising a temperature sensor for the processor, wherein the apparatus is to transmit temperature data from the temperature sensor to the EC via the SPI bus in response to a request for the temperature data from the EC via the SPI bus. 
     
     
         16 . The apparatus of  claim 11 , wherein the apparatus comprises a chip package. 
     
     
         17 . An embedded controller (EC), comprising:
 a first pin coupled to a serial peripheral interface (SPI) bus to receive a message from a chip package when a processor of the chip package enters a low power state; and   a second pin coupled to a fuel gauge of a battery; and   a microcontroller coupled to the first pin and the second pin, wherein the microcontroller, in response to the message, is to determine a discharge rate of the battery and determine based on the discharge rate of the battery whether the processor is in an anomalous low power state.   
     
     
         18 . The EC of  claim 17 , wherein in response to the message, the microcontroller is to request idle state residency data from the chip package via the SPI bus for one or more subsystems, and to determine based on the idle state residency data whether the processor is in the anomalous low power state. 
     
     
         19 . The EC of  claim 17 , wherein in response to the message, the microcontroller is to request internal temperature data from the chip package via the SPI bus, and to determine based on the internal temperature data whether the processor is in the anomalous low power state. 
     
     
         20 . The EC of  claim 17 , wherein the microcontroller is to transmit a message to the chip package via the SPI bus to suspend, restart or shutdown the processor when the processor is in the anomalous low power state.