Embedded metal insulator metal structure

Abstract

The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

What is claimed is: 
     
         1 . A structure, comprising:
 an interconnect structure on a substrate;   a through interposer via (TIV) structure on the interconnect structure;   a dielectric layer on the TIV structure; and   a metal layer on the dielectric layer, wherein a side surface of the metal layer is coplanar with a side surface of the TIV structure.   
     
     
         2 . The structure of  claim 1 , wherein the TIV structure comprises a seed layer and a conductive layer in the seed layer, and wherein a width of a horizontal portion of the seed layer under the conductive layer is equal to a width of the metal layer. 
     
     
         3 . The structure of  claim 2 , wherein the seed layer comprises titanium and copper. 
     
     
         4 . The structure of  claim 2 , wherein a side surface of the dielectric layer is aligned with a side surface of a vertical portion of the seed layer. 
     
     
         5 . The structure of  claim 1 , further comprising:
 an other TIV structure on the interconnect structure, wherein an area of a top surface of the other TIV structure is different from an area of a top surface of the TIV structure; and   an other dielectric layer on the other TIV structure, wherein a side surface of the other dielectric layer is coplanar with a side surface of the other TIV structure.   
     
     
         6 . The structure of  claim 5 , wherein top surfaces of the dielectric layer and the other dielectric layer are coplanar. 
     
     
         7 . The structure of  claim 5 , further comprising a polymer layer between the dielectric layer and the other dielectric layer. 
     
     
         8 . The structure of  claim 5 , further comprising an other metal layer on the other dielectric layer, wherein a width of the other metal layer is the same as a width of the other TIV structure. 
     
     
         9 . The structure of  claim 8 , wherein a first capacitor between the metal layer and the TIV structure and a second capacitor between the other metal layer and the other TIV structure are decoupled. 
     
     
         10 . A structure, comprising:
 an interconnect structure on a substrate;   a through interposer via (TIV) structure on the interconnect structure;   a dielectric layer on the TIV structure;   a metal layer on the dielectric layer, wherein a width of the metal layer is the same as a width of the TIV structure; and   a redistribution layer (RDL) on the metal layer.   
     
     
         11 . The structure of  claim 10 , wherein the dielectric layer comprises a high-k dielectric material with a dielectric constant greater than about 3.9. 
     
     
         12 . The structure of  claim 10 , wherein:
 the substrate comprises a protective layer comprising a polyimide (PI), a polybenzoxazole (PBO), and combinations thereof; and   the interconnect structure comprises metal lines on the protective layer.   
     
     
         13 . The structure of  claim 10 , wherein the RDL comprises:
 a polymer layer on the metal layer; and   a metal line through the polymer layer and in contact with the metal layer.   
     
     
         14 . The structure of  claim 10 , further comprising:
 an under bump metallization (UBM) contact on the RDL; and   a solder bump on the UBM contact.   
     
     
         15 . The structure of  claim 10 , wherein a width of the dielectric layer is the same as the width of the TIV structure. 
     
     
         16 . A structure, comprising:
 an interconnect structure on a substrate;   a through interposer via (TIV) structure on the interconnect structure;   a dielectric layer on the TIV structure, wherein edges of the dielectric layer are aligned with side surfaces of the TIV structure; and   a metal layer on the dielectric layer.   
     
     
         17 . The structure of  claim 16 , further comprising:
 a redistribution layer (RDL) on the metal layer;   an under bump metallization (UBM) contact on the RDL; and   a solder bump on the UBM contact.   
     
     
         18 . The structure of  claim 16 , wherein the metal layer comprises:
 a titanium layer;   a seed layer on the titanium layer; and   a copper layer on the seed layer.   
     
     
         19 . The structure of  claim 16 , wherein a capacitance between the metal layer and TIV structure is between about 10-15 Farad and about 10-9 Farad. 
     
     
         20 . The structure of  claim 16 , wherein edges of the metal layer and TIV structure are aligned with the side surfaces of the TIV structure.