Lead frame substrate having circuitry on dual dielectric layers and assembly using the same

Abstract

A lead frame substrate includes a circuitry layer, terminals, a warpage inhibiting dielectric layer and a stiffening dielectric layer. The circuitry layer extends laterally from the terminals and has an external surface facing away from the stiffening dielectric layer and an inner surface facing in and spaced from a top surface of the stiffening dielectric layer by the warpage inhibiting dielectric layer. The stiffening dielectric layer can serve as a robust platform to support the lateral extension of a circuitry layer and avoid crack propagation through the stiffening dielectric layer into the circuitry layer. The warpage inhibiting dielectric layer can absorb stress and alleviate warpage of the structure during bonding the stiffening dielectric layer to a lead frame with the terminals.

What is claimed is: 
     
         1 . A lead frame substrate, comprising a circuitry layer, terminals, a warpage inhibiting dielectric layer and a stiffening dielectric layer, wherein:
 the stiffening dielectric layer laterally covers and is spaced from lateral surfaces of the terminals by the warpage inhibiting dielectric layer;   the circuitry layer extends laterally from the terminals and is located above and spaced from a top surface of the stiffening dielectric layer by the warpage inhibiting dielectric layer and has an external surface facing away from the stiffening dielectric layer and an inner surface parallel to the external surface and facing in the stiffening dielectric layer;   the warpage inhibiting dielectric layer includes a first interfacial portion between the stiffening dielectric layer and the circuitry layer, a second interfacial portion between the stiffening dielectric layer and the terminals, and a capping portion that extends laterally beyond a periphery of the circuitry layer and covers the top surface of the stiffening dielectric layer; and   the stiffening dielectric layer has a modulus of elasticity higher than that of the warpage inhibiting dielectric layer, wherein the modulus of elasticity of the warpage inhibiting dielectric layer is less than  20  GPa.   
     
     
         2 . The lead frame substrate of  claim 1 , wherein each of the terminals has an external lateral surface at a periphery of the lead frame substrate. 
     
     
         3 . The lead frame substrate of  claim 1 , wherein each of the terminals includes a post portion and a flange portion, and wherein the flange portion extends laterally from the post portion to a periphery of the lead frame substrate, and has a top surface substantially coplanar with the external surface of the circuitry layer and a depression surface located at a predetermined level between the top surface of the flange portion and a bottom surface of the post portion. 
     
     
         4 . The lead frame substrate of  claim 3 , wherein the predetermined level lies between the inner surface of the circuitry layer and the bottom surface of the post portion. 
     
     
         5 . The lead frame substrate of  claim 3 , wherein the warpage inhibiting dielectric layer has inner lateral surfaces adjacent to the depression surface. 
     
     
         6 . The lead frame substrate of  claim 1 , wherein each of the terminals has a bottom surface substantially coplanar with a bottom surface of the stiffening dielectric layer. 
     
     
         7 . The lead frame substrate of  claim 1 , wherein the stiffening dielectric layer is an organic material with a glass reinforcement configured to suppress crack propagation. 
     
     
         8 . The lead frame substrate of  claim 1 , wherein the warpage inhibiting dielectric layer is an organic material with inorganic particle fillers. 
     
     
         9 . The lead frame substrate of  claim 1 , further comprising a thermal pad, wherein the stiffening dielectric layer laterally surrounds and is spaced from lateral surfaces of the thermal pad by a third interfacial portion of the warpage inhibiting dielectric layer. 
     
     
         10 . The lead frame substrate of  claim 9 , wherein the thermal pad has a bottom surface substantially coplanar with a bottom surface of the stiffening dielectric layer. 
     
     
         11 . The lead frame substrate of  claim 9 , wherein the thermal pad has a top surface as a bottom of a recess, and wherein the warpage inhibiting dielectric layer further includes a surrounding portion that is adjacent to the capping portion and the third interfacial portion and laterally surrounds the recess. 
     
     
         12 . A flip chip assembly, comprising:
 the lead frame substrate of  claim 1 ; and   a semiconductor device electrically connected to the lead frame substrate through bumps disposed between the semiconductor device and the circuitry layer of the lead frame substrate.   
     
     
         13 . The flip chip assembly of  claim 12 , further comprising a sealing material encapsulating the semiconductor device and extending laterally to a periphery of the flip chip assembly. 
     
     
         14 . The flip chip assembly of  claim 12 , wherein (i) the lead frame substrate further comprises a thermal pad, (ii) the stiffening dielectric layer laterally surrounds and is spaced from lateral surfaces of the thermal pad by a third interfacial portion of the warpage inhibiting dielectric layer, and (iii) the semiconductor device is superimposed over and thermally conductible with the thermal pad through additional bumps between the semiconductor device and the thermal pad. 
     
     
         15 . A wire bond assembly, comprising:
 the lead frame substrate of  claim 9 ; and   a semiconductor device superimposed over and thermally conductible with the thermal pad and electrically connected to the circuitry layer of the lead frame substrate through bonding wires.   
     
     
         16 . The wire bond assembly of  claim 15 , wherein (i) the thermal pad has a top surface as a bottom of a recess, (ii) the warpage inhibiting dielectric layer further includes a surrounding portion that is adjacent to the capping portion and the third interfacial portion and laterally surrounds the recess, and (iii) the semiconductor device is disposed in the recess and laterally surrounded by the surrounding portion of the warpage inhibiting dielectric layer.