Semiconductor device having through via and method of fabricating thereof

Abstract

Semiconductor structures and methods for forming the same that include a through substrate via. Sacrificial gate structures are formed concurrently with active gate structures, the sacrificial gate structures being disposed in a through via region of the substrate. The sacrificial gate structures are subsequently removed from the substrate and dielectric material formed in their place. The through substrate via extends through the dielectric material.

What is claimed is: 
     
         1 . A method of semiconductor device fabrication, the method comprising:
 forming a first plurality of gate structures over a first region of a substrate and a second plurality of gate structures over a second region of the substrate;   forming a first opening by removing at least one of the second plurality of gate structures in the second region of the substrate;   filling the first opening with a first dielectric material;   forming an interconnect layer over the first plurality of gate structures and the first dielectric material;   etching a second opening through the interconnect layer, the first dielectric material, and through at least a portion of the second region of the substrate; and   forming a via structure within the second opening, the via structure extending through the interconnect layer, the first dielectric material, and the second region of the substrate.   
     
     
         2 . The method of semiconductor device fabrication of  claim 1 , wherein the forming the first plurality of gate structures and the second plurality of gate structures includes:
 forming polysilicon gate structures:   removing the polysilicon gate structures to form a trench; and   forming a metal gate electrode in the trench.   
     
     
         3 . The method of semiconductor device fabrication of  claim 1 , wherein the first dielectric material is silicon nitride. 
     
     
         4 . The method of semiconductor device fabrication of  claim 3 , wherein the forming the interconnect layer includes forming an intermetal dielectric (IMD) layer and a metal interconnect layer. 
     
     
         5 . The method of semiconductor device fabrication of  claim 4 , wherein the IMD layer comprises a second dielectric material different than the first dielectric material. 
     
     
         6 . The method of semiconductor device fabrication of  claim 1 , wherein concurrent with the forming the first opening, forming a third opening providing a cut-gate region in a first gate of the first plurality of gate structures in the first region of the substrate. 
     
     
         7 . The method of semiconductor device fabrication of  claim 6 , further comprising:
 concurrently with filling the first opening, filling the third opening with the first dielectric material.   
     
     
         8 . The method of semiconductor device fabrication of  claim 1 , further comprising:
 forming an interlayer dielectric (ILD) layer adjacent and interposing the first plurality of gate structures and adjacent and interposing the second plurality of gate structures.   
     
     
         9 . The method of semiconductor device fabrication of  claim 8 , wherein the ILD layer is silicon oxide and the first dielectric material is silicon nitride. 
     
     
         10 . The method of semiconductor device fabrication of  claim 1 , wherein after the forming of the via structure, the first dielectric material remains abutting sidewalls of the via structure. 
     
     
         11 . A method of forming a semiconductor device, comprising:
 forming a first plurality of metal gates on a substrate;   providing an interlayer dielectric (ILD) adjacent the metal gates;   etching a first opening and a second opening, wherein the first opening extends into the ILD and through a first metal gate and a second metal gate of the first plurality of metal gates and the second opening extends through a third metal gate of the first plurality of metal gates to form a gate cut region;   filling the first opening and the second opening with a dielectric material;   after the filling the first opening and the second opening, depositing an interconnect layer over the substrate;   etching the interconnect layer to form a via opening, wherein the via opening extends through the dielectric material; and   depositing conductive material in the via opening to form a via structure.   
     
     
         12 . The method of  claim 11 , further comprising:
 thinning a backside of the substrate to expose the via structure.   
     
     
         13 . The method of  claim 11 , wherein sidewalls of the via structure interface the dielectric material. 
     
     
         14 . The method of  claim 11 , further comprising:
 depositing a hard mask layer over the ILD and the first plurality of metal gate; and   defining a pattern of the first opening and the second opening in the hard mask layer.   
     
     
         15 . The method of  claim 11 , wherein the first opening is formed over a shallow trench isolation structure disposed on the substrate. 
     
     
         16 . The method of  claim 11 , wherein the forming the first plurality of metal gates includes forming the first plurality of metal gates over fin-type active regions extending from the substrate. 
     
     
         17 . A semiconductor structure, comprising:
 a substrate;   a plurality of gate structures disposed on the substrate;   a multi-layer interconnect (MLI) disposed over the substrate and the plurality of gate structures;   a through substrate via extending vertically through the substrate and the MLI, wherein the through substrate via has a first sidewall in a cross-sectional view, wherein the first sidewall includes:   an upper portion interfacing a first dielectric material of the MLI;   a middle portion interfacing a second dielectric material, the second dielectric material different than the first dielectric material; and   a lower portion interfacing the substrate.   
     
     
         18 . The semiconductor structure of  claim 17 , wherein the second dielectric material surrounds the middle portion of the through substrate via in a top view. 
     
     
         19 . The semiconductor structure of  claim 17 , wherein the first dielectric material is an oxide and the second dielectric material is silicon nitride. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein at least part of the middle portion of the first sidewall is coplanar with the plurality of gate structures.