Semiconductor structure and method for fabricating the same

Abstract

A semiconductor structure includes a substrate and a first switch element disposed in a first device area of the substrate. The first switch element includes a channel region, a first gate dielectric layer, a first gate layer and a source/drain region. The channel region is disposed at the bottom of a recess in the first device area. The first gate dielectric layer has a first region and a second region extending into the recess, the first region has a first thickness; the second region has a second thickness, and the first thickness is smaller than the second thickness. The first gate layer is disposed above the first gate dielectric layer. The source/drain region is disposed in the substrate and adjacent to the first gate dielectric layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate; and   a first switch element, disposed in a first device area of the substrate, comprising:
 a channel region, disposed at a bottom of a recess in the first device area; 
 a first gate dielectric layer, having a first region and a second region extending into the recess; wherein the first region has a first thickness; the second region has a second thickness; and the first thickness is smaller than the second thickness; 
 a first gate layer, disposed above the first gate dielectric layer; and 
 a source/drain region, disposed in the substrate and adjacent to the first gate dielectric layer. 
   
     
     
         2 . The semiconductor structure according to  claim 1 , wherein the recess extends into the substrate from a substrate surface; and the first region has a first top surface lower than the substrate surface of the substrate. 
     
     
         3 . The semiconductor structure according to  claim 2 , wherein the second region has a second top surface; and the first gate dielectric layer comprises an arc surface connecting the first top surface and the second top surface. 
     
     
         4 . The semiconductor structure according to  claim 3 , wherein the second top surface is higher than the substrate surface. 
     
     
         5 . The semiconductor structure according to  claim 2 , further comprises a second switch element disposed in a second device area of the substrate, wherein the second switch element comprises a second gate dielectric layer that has a material the same to that of the first gate dielectric layer and the first thickness. 
     
     
         6 . A method for fabricating a semiconductor structure, comprising:
 forming a recess in a first device area of a substrate;   forming a channel region at a bottom of the recess;   forming a first gate dielectric layer having a first region and a second region to extend into the recess, wherein the first region has a first thickness; the second region has a second thickness, and the first thickness is smaller than the second thickness;   forming a first gate layer above the first gate dielectric layer; and   forming a source/drain region in the substrate and adjacent to the first gate dielectric layer.   
     
     
         7 . The method according to  claim 6 , wherein the step of forming the first gate dielectric layer comprises:
 forming a first dielectric material layer having an initial thickness and extending into the recess;   etching the first dielectric material layer to remove a portion of the first dielectric material layer disposed in the first region to form an opening; and forming a second dielectric material layer at least covering the first region.   
     
     
         8 . The method according to  claim 7 , wherein the step of forming the recess in the substrate comprises performing an etching process to remove a portion of the substrate, so as to form the recess extending downward into the substrate from a substrate surface of the substrate. 
     
     
         9 . The method according to  claim 8 , wherein after the second dielectric material layer is formed, a portion of the second dielectric material layer disposed in the first region has a first top surface lower than the substrate surface; a portion of the second dielectric material layer disposed in the second region has a second top surface higher than the substrate surface. 
     
     
         10 . The method according to  claim 7 , wherein the step of etching the first dielectric material layer comprises removing the portion of the first dielectric material layer disposed in the first region to make a portion of the substrate exposed from the opening. 
     
     
         11 . The method according to  claim 10 , wherein the first thickness is equal to a thickness of the second dielectric material layer, and the second thickness is equal to a total thickness of the first dielectric material layer and the second dielectric material layer. 
     
     
         12 . The method according to  claim 6 , wherein a portion of the second dielectric material layer covers a second device area of the substrate and serves as a second gate dielectric layer of a second switch element. 
     
     
         13 . A semiconductor structure, comprising:
 a substrate; and   a first transistor, disposed in the substrate, and comprising a first gate dielectric layer, wherein the first gate dielectric layer has a first region with a first thickness and a second region with a second thickness; and   a second transistor, disposed in the substrate, and comprising a second gate dielectric layer with a third thickness;   wherein the second thickness is greater than the first thickness; and the first thickness is substantially equal to the third thickness.   
     
     
         14 . The semiconductor structure according to  claim 13 , wherein the first transistor is a high voltage transistor; and the second transistor is a low voltage transistor or a core device. 
     
     
         15 . The semiconductor structure according to  claim 13 , wherein the third thickness of the second gate dielectric layer is less than or equal to 15 angstrom (Å). 
     
     
         16 . The semiconductor structure according to  claim 13 , wherein the first transistor is a high voltage transistor; the second transistor is an I/O device; and the third thickness is less than or equal to 25 Å. 
     
     
         17 . The semiconductor structure according to  claim 13 , wherein the first transistor has a drift region, the second transistor has a lightly doped drain (LDD) region; wherein the drift region has a first depth, and the LDD region has a second depth; the first depth is greater than the second depth. 
     
     
         18 . The semiconductor structure according to  claim 13 , wherein the first transistor has a first gate layer, the second transistor has a second gate layer; the first gate layer and the second gate layer both comprise a metal conductive material or both comprise a non-metal conductive material. 
     
     
         19 . The semiconductor structure according to  claim 13 , wherein the first transistor has a first gate layer, the second transistor has a second gate layer; the first gate layer comprises a non-metal conductive material; and the second gate layer comprises a metal conductive material. 
     
     
         20 . The semiconductor structure according to  claim 13 , wherein the second gate dielectric layer of the second transistor has a top surface higher than a substrate surface of the substrate.