Em and rf mitigation silicon structures in stacked die microprocessors for die to platform and die-die rf noise suppression

Abstract

Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

What is claimed is: 
     
         1 . An electronic package comprising:
 a package substrate;   a base substrate over the package substrate;   a plurality of chiplets over the substrate; and   a Faraday's cage around at least one of the plurality of chiplets.   
     
     
         2 . The electronic package of  claim 1 , wherein the Faraday's cage comprises:
 a conductive mesh over a backside surface of the at least one of the plurality of chiplets, wherein the conductive mesh is grounded.   
     
     
         3 . The electronic package of  claim 1 , wherein the Faraday's cage comprises a conductive mesh in a metal layer of the base substrate over a front side surface of the at least one of the plurality of chiplets. 
     
     
         4 . The electronic package of  claim 1 , wherein the Faraday's cage comprises through substrate vias in the base substrate. 
     
     
         5 . The electronic package of  claim 4 , wherein the through substrate vias surround an interconnect in the base substrate between a first chiplet and a second chiplet. 
     
     
         6 . The electronic package of  claim 4 , wherein the through substrate vias surround a perimeter of the at least one of the plurality of chiplets. 
     
     
         7 . An electronic system, comprising:
 a board; and   an electronic package coupled to the board, the electronic package comprising:
 a package substrate; 
 a base substrate over the package substrate; 
 a plurality of chiplets over the substrate; and 
 a Faraday's cage around at least one of the plurality of chiplets. 
   
     
     
         8 . The electronic system of  claim 7 , wherein the Faraday's cage of the electronic package comprises:
 a conductive mesh over a backside surface of the at least one of the plurality of chiplets, wherein the conductive mesh is grounded.   
     
     
         9 . The electronic system of  claim 7 , wherein the Faraday's cage of the electronic package comprises a conductive mesh in a metal layer of the base substrate over a front side surface of the at least one of the plurality of chiplets. 
     
     
         10 . The electronic system of  claim 7 , wherein the Faraday's cage of the electronic package comprises through substrate vias in the base substrate. 
     
     
         11 . The electronic system of  claim 7 , further comprising:
 a memory chip coupled to the board.   
     
     
         12 . The electronic system of  claim 7 , further comprising:
 a communications chip coupled to the board.   
     
     
         13 . The electronic system of  claim 7 , further comprising:
 a battery coupled to the board.   
     
     
         14 . The electronic system of  claim 7 , further comprising:
 a camera coupled to the board.   
     
     
         15 . A method of fabricating an electronic package, the method comprising:
 forming a package substrate;   providing a base substrate over the package substrate;   providing a plurality of chiplets over the substrate; and   forming a Faraday's cage around at least one of the plurality of chiplets.   
     
     
         16 . The method of  claim 15 , wherein forming the Faraday's cage comprises:
 forming a conductive mesh over a backside surface of the at least one of the plurality of chiplets, wherein the conductive mesh is grounded.   
     
     
         17 . The method of  claim 15 , wherein forming the Faraday's cage comprises forming a conductive mesh in a metal layer of the base substrate over a front side surface of the at least one of the plurality of chiplets. 
     
     
         18 . The method of  claim 15 , wherein the Faraday's cage comprises through substrate vias in the base substrate. 
     
     
         19 . The method of  claim 18 , wherein the through substrate vias surround an interconnect in the base substrate between a first chiplet and a second chiplet. 
     
     
         20 . The method of  claim 18 , wherein the through substrate vias surround a perimeter of the at least one of the plurality of chiplets.