Manufacturing method of semiconductor device with inductor

Abstract

A manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.

What is claimed is: 
     
         1 . A manufacturing method of a semiconductor device, comprising:
 disposing a first conductive material to form first inductor traces extending parallel to each other along a first direction and at a distance from each other along a second direction;   forming a first dielectric layer on the first inductor traces, wherein the first dielectric layer comprises first openings exposing opposite ends of the first inductor traces;   blanketly disposing a buffer material on the first dielectric layer and on the first inductor traces in the first openings;   blanketly disposing an etch stop material on the buffer material;   blanketly disposing a ferromagnetic material on the etch stop material;   removing the ferromagnetic material from over the first openings to form a core material layer covering a first area overlapping the first inductor traces;   removing the etch stop material and the buffer material from the first openings to respectively form an etch stop layer and a buffer layer, wherein the etch stop layer and the buffer layer cover a second area overlapping the first inductor traces, and the first area is smaller than and is contained within the second area;   forming a second dielectric layer on the first dielectric layer to embed the buffer layer, the etch stop layer, and the core material layer; and   disposing a second conductive material to form upper inductor traces extending on the second dielectric layer and inductor vias extending through the first dielectric layer and the second dielectric layer to connect the upper inductor traces with the first inductor traces.   
     
     
         2 . The manufacturing method of  claim 1 , wherein forming the core material layer comprises:
 forming an auxiliary mask on the ferromagnetic material covering the first area; and   etching away the ferromagnetic material left exposed by the auxiliary mask.   
     
     
         3 . The manufacturing method of  claim 1 , wherein forming the buffer layer and the etch stop layer comprises:
 forming an auxiliary mask on the etch stop material covering the second area, wherein the auxiliary mask covers a top surface and edges of the core material layer; and   etching away the etch stop material and the buffer material left exposed by the auxiliary mask.   
     
     
         4 . The manufacturing method of  claim 1 , wherein forming the second dielectric layer comprises patterning a dielectric material to form second openings wider than the first openings, wherein the first openings extend through the first dielectric layer from a bottom of the second openings. 
     
     
         5 . The manufacturing method of  claim 4 , wherein forming the upper inductor traces comprises:
 forming second inductor traces, extending along a third direction different than the first direction and the second direction, wherein opposite ends of the second inductor traces contact inductor vias landing on adjacent first inductor traces; and   forming a pair of inductor terminal traces, each inductor terminal trace contacting at one end a corresponding inductor via landing on a corresponding outermost first inductor trace.   
     
     
         6 . The manufacturing method of  claim 1 , further comprising:
 laterally covering a semiconductor die with an encapsulant before disposing the first conductive material to form the first inductor traces, wherein the first inductor traces and the first dielectric layer are formed over the semiconductor die and the encapsulant.   
     
     
         7 . The manufacturing method of  claim 6 , wherein the semiconductor die comprises a semiconductor substrate, a protective layer formed over the semiconductor substrate, and contact posts formed over the semiconductor substrate and laterally surrounded by the protective layer, wherein laterally covering the semiconductor die with the encapsulant comprises:
 performing a planarization process on the semiconductor die and the encapsulant to level surfaces of the protective layer, the contact posts, and the encapsulant.   
     
     
         8 . The manufacturing method of  claim 6 , further comprising:
 forming a redistribution structure over the semiconductor die and the encapsulant, wherein the first inductor traces, the inductor vias, the etch stop layer, the buffer layer, and the core material layer are embedded in the redistribution structure, wherein the first and second dielectric layers are parts of the redistribution structure.   
     
     
         9 . The manufacturing method of  claim 6 , further comprising:
 forming the buffer layer, the etch stop layer, and the core material layer directly over the encapsulant.   
     
     
         10 . The manufacturing method of  claim 1 , wherein the etch stop material comprises cobalt, tantalum, an oxide thereof, or a combination thereof. 
     
     
         11 . The manufacturing method of  claim 1 , wherein the buffer material comprises silicon, silicon nitride, or a combination thereof. 
     
     
         12 . A manufacturing method of a semiconductor device, comprising:
 laterally covering a semiconductor die with an encapsulant; and   forming a redistribution structure over the semiconductor die and the encapsulant, wherein forming the redistribution structure comprises:
 forming conductive patterns in dielectric layers, wherein the conductive patterns comprises an inductor pattern; and 
 forming a core covered by the dielectric layers, wherein the core comprises a buffer layer, an etch stop layer, and a core material layer sequentially stacked, the inductor pattern wound around the core, and a total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. 
   
     
     
         13 . The manufacturing method of  claim 12 , wherein the core material layer comprises a ferromagnetic material. 
     
     
         14 . The manufacturing method of  claim 12 , wherein forming the inductor pattern comprises:
 forming first inductor spiral traces before forming the core;   forming inductor vias at the sides of the core and connecting the first inductor spiral traces; and   forming second inductor spiral traces on the inductor vias, wherein the second inductor spiral traces extend at an angle with respect to the first inductor spiral traces.   
     
     
         15 . The manufacturing method of  claim 12 , wherein forming the core comprises:
 forming the buffer layer, the etch stop layer, and a core material layer vertically and laterally offset from the semiconductor die.   
     
     
         16 . The manufacturing method of  claim 12 , wherein forming the core comprises:
 forming the etch stop layer horizontally protruding with respect to the core material layer, wherein a vertical projection of the core material layer falls entirely on the etch stop layer.   
     
     
         17 . A manufacturing method of a semiconductor device, comprising:
 forming an encapsulated die; and   forming a redistribution structure over the encapsulated die, wherein forming the redistribution structure comprises:
 forming a core, wherein the core comprises a buffer layer, an etch stop layer, and a core material layer sequentially stacked, a side edge of the etch stop layer is laterally protruded from a side edge of the core material layer, and the side edge of the etch stop layer is vertically aligned with a side edge of the buffer layer; and 
 forming an inductor pattern wound around the core, wherein the inductor pattern comprises spiral traces and spiral vias connected to the spiral traces. 
   
     
     
         18 . The manufacturing method of  claim 17 , wherein the core material layer comprises a ferromagnetic material. 
     
     
         19 . The manufacturing method of  claim 17 , wherein forming the core comprises:
 forming the etch stop layer on the buffer layer, wherein a vertical projection of the etch stop layer coincides with a total area occupied by the buffer layer.   
     
     
         20 . The manufacturing method of  claim 17 , wherein forming the core comprises:
 forming the core material layer on the etch stop layer, wherein a total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer, and the etch stop layer horizontally protrudes with respect to the core material layer.