Semiconductor structure

Abstract

A semiconductor structure includes a gate, an active layer, a gate insulator layer, a source, and a drain. The active layer has a source region, a drain region, and a channel region. The semiconductor structure satisfies at least one of the following conditions: (1) a material of the active layer includes a-Si, and a first thickness and a second thickness of the active layer respectively in the source region and the drain region are respectively greater than a third thickness of the active layer in the channel region; (2) the gate insulator layer includes a first gate insulator layer, a third gate insulator layer, and a second gate insulator layer located between the first and third gate insulator layers. A material of the first gate insulator layer is identical to a material of the third gate insulator layer but different from a material of the second gate insulator layer.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a gate;   an active layer, disposed on the gate and having a source region, a drain region, and a channel region located between the source region and the drain region;   a gate insulator layer, disposed between the gate and the active layer;   a source, disposed above the source region and extending onto the gate insulator layer; and   a drain, disposed above the drain region and extending onto the gate insulator layer,   wherein the semiconductor structure at least satisfies one of following conditions:   (1) a material of the active layer comprises amorphous silicon, and a first thickness of the active layer in the source region and a second thickness of the active layer in the drain region are respectively greater than a third thickness of the active layer in the channel region;   (2) the gate insulator layer comprises a first gate insulator layer, a second gate insulator layer, and a third gate insulator layer, the second gate insulator layer is located between the first gate insulator layer and the third gate insulator layer, and a material of the first gate insulator layer is the same as a material of the third gate insulator layer, while a material of the second gate insulator layer is different from the material of the first gate insulator layer.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein the first thickness is equal to the second thickness, the third thickness is less than the first thickness, and the third thickness is less than 1500 angstroms. 
     
     
         3 . The semiconductor structure as claimed in  claim 1 , wherein the first gate insulator layer has a first insulation thickness, the second gate insulator layer has a second insulation thickness, the third gate insulator layer has a third insulation thickness, and the second insulation thickness is less than the first insulation thickness and the third insulation thickness. 
     
     
         4 . The semiconductor structure as claimed in  claim 3 , wherein the first insulation thickness is greater than the third insulation thickness. 
     
     
         5 . The semiconductor structure as claimed in  claim 1 , wherein the second gate insulator layer is a plasma treatment layer. 
     
     
         6 . The semiconductor structure as claimed in  claim 5 , wherein a material of the plasma treatment layer comprises silicon oxide, aluminum oxide, or titanium oxide. 
     
     
         7 . The semiconductor structure as claimed in  claim 1 , wherein a material of the first gate insulator layer and a material of the third gate insulator layer comprise silicon nitride, respectively. 
     
     
         8 . The semiconductor structure as claimed in  claim 1 , wherein the first gate insulator layer, the second gate insulator layer, and the third gate insulator layer are sequentially stacked on the gate. 
     
     
         9 . The semiconductor structure as claimed in  claim 8 , wherein the first gate insulator layer, the second gate insulator layer, and the third gate insulator layer are arranged in a coplanar manner. 
     
     
         10 . The semiconductor structure as claimed in  claim 1 , further comprising:
 an ohmic contact layer, disposed between the source region of the active layer and the source and between the drain region of the active layer and the drain.