Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes: an active pattern provided on a substrate and enclosed by a device isolation pattern; and a word line crossing the active pattern and the device isolation pattern in a first direction parallel to a bottom surface of the substrate, and including a first gate electrode and a second gate electrode, which are adjacent to each other in the first direction. A second work function of the second gate electrode is greater than a first work function of the first gate electrode.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 an active pattern provided on a substrate and enclosed by a device isolation pattern; and   a word line crossing the active pattern and the device isolation pattern in a first direction parallel to a bottom surface of the substrate, and comprising a first gate electrode and a second gate electrode, which are adjacent to each other in the first direction,   wherein a second work function of the second gate electrode is greater than a first work function of the first gate electrode.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein a first side surface of the first gate electrode faces the first direction, and
 wherein the second gate electrode is on the first side surface of the first gate electrode.   
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the word line comprises a pair of word lines crossing the active pattern in the first direction, and
 wherein the first gate electrode of a first one of the pair of word lines and the second gate electrode of a second one of the pair of word lines are adjacent to each other in a second direction crossing the first direction.   
     
     
         4 . The semiconductor memory device of  claim 1 , wherein the word line is a first word line,
 wherein the active pattern is a first active pattern,   wherein the semiconductor memory device further comprises:
 a second word line, which is adjacent to the first word line in a second direction crossing the first direction; and 
 a second active pattern, which is adjacent to the first active pattern in a third direction crossing the first and second directions, and 
   wherein the second gate electrode of the second word line is interposed between the first active pattern and the second active pattern.   
     
     
         5 . The semiconductor memory device of  claim 1 , wherein the first gate electrode comprises a plurality of first gate electrodes,
 wherein the second gate electrode comprises a plurality of second gate electrodes, and   wherein the plurality of first gate electrodes and the plurality of second gate electrodes are alternately disposed in the first direction.   
     
     
         6 . The semiconductor memory device of  claim 1 , wherein a top surface of the second gate electrode is located at a level, which is equal to or higher than a top surface of the first gate electrode along a vertical direction perpendicular to the bottom surface of the substrate. 
     
     
         7 . The semiconductor memory device of  claim 1 , wherein a bottom surface of the second gate electrode is in contact with the device isolation pattern. 
     
     
         8 . The semiconductor memory device of  claim 1 , wherein the first gate electrode and the second gate electrode comprise different materials, each of which comprises at least one of Ti, TiN, TiSiN, TiON, W, WN, Mo, MON, MoO x N y , Ta, TaN, or poly Si. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein the second gate electrode has a resistivity smaller than the first gate electrode. 
     
     
         10 . The semiconductor memory device of  claim 1 , further comprising a third gate electrode on the first gate electrode,
 wherein a third work function of the third gate electrode is smaller than the first work function of the first gate electrode.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein the third gate electrode extends from a top surface of the first gate electrode to a region on a top surface of the second gate electrode. 
     
     
         12 . The semiconductor memory device of  claim 10 , wherein the second gate electrode comprises a plurality of second gate electrodes, which are adjacent to each other in the first direction, and
 wherein the third gate electrode is interposed between adjacent ones of the plurality of second gate electrodes.   
     
     
         13 . The semiconductor memory device of  claim 10 , wherein a top surface of the second gate electrode is located at a level, which is equal to or higher than a top surface of the third gate electrode along a vertical direction perpendicular to the bottom surface of the substrate. 
     
     
         14 . A semiconductor memory device, comprising:
 an active pattern provided on a substrate and enclosed by a device isolation pattern;   a first gate electrode crossing the active pattern and the device isolation pattern in a first direction parallel to a bottom surface of the substrate; and   a second gate electrode extending through the first gate electrode along a vertical direction perpendicular to the bottom surface of the substrate,   wherein the first gate electrode is provided around a side surface of the second gate electrode, and   wherein a second work function of the second gate electrode is greater than a first work function of the first gate electrode.   
     
     
         15 . The semiconductor memory device of  claim 14 , wherein the second gate electrode is spaced apart from the device isolation pattern by the first gate electrode. 
     
     
         16 . The semiconductor memory device of  claim 14 , wherein a top surface of the first gate electrode has a first width in a second direction crossing the first direction,
 wherein a top surface of the second gate electrode has a second width in the second direction, and   wherein the first width is larger than the second width.   
     
     
         17 . The semiconductor memory device of  claim 14 , further comprising a third gate electrode on the first gate electrode,
 wherein a top surface of the third gate electrode has a third width in a second direction crossing the first direction,   wherein a top surface of the second gate electrode has a second width in the second direction, and   wherein the third width is larger than the second width.   
     
     
         18 . The semiconductor memory device of  claim 14 , wherein a top surface of the second gate electrode is located at a level, which is equal to or higher than a top surface of the first gate electrode along the vertical direction. 
     
     
         19 . The semiconductor memory device of  claim 14 , wherein the first gate electrode comprises a first region, which is adjacent to the second gate electrode in the first direction, and a second region, which is adjacent to the second gate electrode in a second direction crossing the first direction, and
 wherein, along the vertical direction, a bottom surface of the second gate electrode is located at a level, which is equal to or lower than a bottom surface of the first region and is lower than a bottom surface of the second region.   
     
     
         20 . A semiconductor memory device, comprising:
 an active pattern provided on a substrate and enclosed by a device isolation pattern;   a word line crossing the active pattern and the device isolation pattern in a first direction parallel to a bottom surface of the substrate, the word line comprising a first gate electrode and a second gate electrode, which are adjacent to each other in the first direction;   a bit line provided on the active pattern and extended in a second direction crossing the first direction;   a bit line contact between the active pattern and the bit line;   a storage node contact on the active pattern;   a landing pad on the storage node contact; and   a data storage pattern on the landing pad,   wherein a second work function of the second gate electrode is greater than a first work function of the first gate electrode.