High electron mobility transistor and method for manufacturing the same

Abstract

A high electron mobility transistor includes a body, a transistor unit, and an electrically conducting structure. The body has a first surface and a second surface opposite to the first surface. The transistor unit includes a composite semiconductor layer disposed on the first surface and an electrode component disposed on the composite semiconductor layer opposite to the first surface. The electrode component includes a gate electrode, a source electrode, and a drain electrode which are spaced apart from one another. The source electrode and the drain electrode are disposed at two opposite sides of the gate electrode. The electrically conducting structure includes a back electrode disposed on the second surface and at least one connecting electrode connecting the gate electrode and the back electrode. A method for manufacturing the high electron mobility transistor is also provided herein.

What is claimed is: 
     
         1 . A high electron mobility transistor, comprising:
 a body having a first surface and a second surface opposite to said first surface;   a transistor unit including a composite semiconductor layer disposed on said first surface and an electrode component disposed on said composite semiconductor layer opposite to said first surface, said electrode component including a gate electrode, a source electrode, and a drain electrode which are spaced apart from one another, said source electrode and said drain electrode disposed at two opposite sides of said gate electrode; and   an electrically conducting structure including a back electrode disposed on said second surface and at least one connecting electrode connecting said gate electrode and said back electrode.   
     
     
         2 . The high electron mobility transistor as claimed in  claim 1 , wherein said body further includes two opposite side surfaces each of which connects said first surface and said second surface, said at least one connecting electrode being disposed on one of said side surfaces and said composite semiconductor layer. 
     
     
         3 . The high electron mobility transistor as claimed in  claim 1 , wherein said composite semiconductor layer includes a buffer layer disposed on said first surface and a barrier layer disposed on said buffer layer opposite to said first surface, said electrode component being disposed on said barrier layer. 
     
     
         4 . The high electron mobility transistor as claimed in  claim 3 , wherein said body is made of aluminum oxide. 
     
     
         5 . The high electron mobility transistor as claimed in  claim 3 , wherein said buffer layer is made of gallium nitride. 
     
     
         6 . The high electron mobility transistor as claimed in  claim 3 , wherein said barrier layer is made of aluminum gallium nitride. 
     
     
         7 . The high electron mobility transistor as claimed in  claim 1 , wherein said body is formed with a recess which corresponds in position with said transistor unit, said second surface having an inner recess portion that defines said recess and an outer surface portion connected to a periphery of said inner recess portion, said back electrode including a thermally conducting portion disposed on said inner recess portion, and a grounding portion connected to said thermally conducting portion, disposed on said outer surface portion and electrically connected to said at least one connecting electrode. 
     
     
         8 . The high electron mobility transistor as claimed in  claim 7 , wherein said body is made of aluminum oxide. 
     
     
         9 . The high electron mobility transistor as claimed in  claim 7 , wherein said inner recess portion of said second surface is separated from said first surface by a minimum distance ranging from 1 μm to 30 μm. 
     
     
         10 . A method for manufacturing a high electron mobility transistor, comprising the steps of:
 a) providing a transistor wafer that includes a substrate and a plurality of transistor units that are disposed on the substrate and that are spaced apart from one another, the substrate being defined to have a plurality of dicing lanes, any two adjacent ones of the transistor units being spaced apart from each other by a respective one of the dicing lanes, each of the transistor units including a gate electrode;   b) forming at least one first electrically conducting portion on each of the transistor units, the at least one first electrically conducting portion being connected to the gate electrode and extending into an adjacent one of the dicing lanes;   c) forming an electrically conducting layer on the substrate opposite to the transistor units;   d) providing a connecting element on the electrically conducting layer opposite to the substrate, followed by removing portions of the substrate and the electrically conducting layer which correspond in position with the dicing lanes, so as to form the substrate into a plurality of bodies on which the transistor units are respectively disposed, and to form the electrically conducting layer into a plurality of back electrodes that are respectively disposed on the bodies and that are disposed on the connecting element to be spaced apart from each other;   e) forming at least one second electrically conducting portion on each of the bodies, the at least one second electrically conducting portion being electrically connected to the back electrode and the at least one first electrically conducting portion of a corresponding one of the transistor units; and   f) removing the connecting element so as to obtain a plurality of the high electron mobility transistors.   
     
     
         11 . The method as claimed in  claim 10 , further comprising, after step b) and before step c), forming the substrate with a plurality of recesses that are indented from a surface of the substrate opposite to the transistor units toward the transistor units and that correspond in position with the transistor units, respectively, in step c), the electrically conducting layer being formed on the surface of the substrate where the recesses are formed. 
     
     
         12 . The method as claimed in  claim 10 , wherein,
 in step d), the connecting element is made of a stretchable material, and   the method further includes, after step d) and before step e), stretching the connecting element so as to increase a spacing between two adjacent ones of the bodies.   
     
     
         13 . The method as claimed in  claim 10 , wherein in step d), before removal of the portions of the substrate and the electrically conducting layer, a mask layer is formed to respectively cover the transistor units and portions of the first electrically conducting portions, and to expose the dicing lanes. 
     
     
         14 . The method as claimed in  claim 10 , wherein in step d), removal of the portions of the substrate and the electrically conducting layer is conducted using a dicing technique, and is started from the dicing lanes toward the connecting element.