Semiconductor Device Package with Die Stackup and Interposer

Abstract

A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.

What is claimed is: 
     
         1 . A semiconductor device package comprising:
 a substrate having a first set of bond pads electrically connected thereto;   a stack of semiconductor dies including a first sub-stack of dies and a second sub-stack of dies, the second sub-stack of dies positioned above the first sub-stack of dies;   an interposer positioned on the substrate and spaced from the stack of semiconductor dies;   a second set of bond pads positioned on the interposer and electrically connected to the substrate by way of the interposer, wherein the second set of bond pads are positioned above the substrate;   a first set of bond wires electrically connecting the first sub-stack of dies to the first set of bond pads; and   a second set of bond wires electrically connecting the second sub-stack of dies to the second set of bond pads.   
     
     
         2 . The semiconductor device package of  claim 1 , wherein the stacked semiconductor dies comprise memory dies, and the first sub-stack of memory dies and second sub-stack of memory dies are electrically isolated from one another. 
     
     
         3 . The semiconductor device package of  claim 1 , wherein the first set of bond pads is positioned on the substrate between the stack of semiconductor dies and the interposer. 
     
     
         4 . The semiconductor device package of  claim 1 , wherein the second set of bond pads are positioned above a top surface of the substrate by a height of at least 50 microns. 
     
     
         5 . The semiconductor device package of  claim 1 , wherein a height of the interposer is at least five times a diameter of bond wires included in the first or second sets of bond wires. 
     
     
         6 . The semiconductor device package of  claim 1 , wherein at least a portion of the second set of bond wires is positioned vertically above the first set of bond wires and does not directly contact the first set of bond wires. 
     
     
         7 . The semiconductor device package of  claim 1 , wherein the interposer is comprised of a dielectric material. 
     
     
         8 . The semiconductor device package of  claim 1 , wherein the second set of bond pads is electrically connected to the substrate by a through-device via in the interposer. 
     
     
         9 . The semiconductor device package of  claim 8  further comprising:
 one or more solder balls physically coupling the interposer to the substrate and electrically connecting the through-device via to the substrate. 
 
     
     
         10 . The semiconductor device package of  claim 1 , wherein the substrate includes a third set of bond pads,
 wherein the interposer is positioned between the first and third sets of bond pads, and   wherein the semiconductor device package further comprises a third set of bond wires electrically connecting to the second set of bond pads to the third set of bond pads.   
     
     
         11 . The semiconductor device package of  claim 10 , wherein the interposer is mounted directly on the substrate. 
     
     
         12 . The semiconductor device package of  claim 1 , wherein each semiconductor die included in the stack of semiconductor dies includes a set of die bond pads, wherein the die bond pads of the first sub-stack of dies are electrically connected to the first set of bond pads by the first set of bond wires, and the die bond pads of the second sub-stack of dies are electrically connected to the second set of bond pads by the second set of bond wires. 
     
     
         13 . A semiconductor memory package comprising:
 a substrate including a top surface and a first set of bond pads exposed at the top surface;   an interposer positioned on and extending upwardly from the top surface of the substrate, the interposer including a second set of bond pads coupled to a top surface of the interposer;   a stack of staggered memory dies offset with respect to each other in a longitudinal direction and including a bottom sub-stack of memory dies and an upper sub-stack of memory dies;   a first plurality of bond wires electrically connecting the bottom sub-stack of memory dies to the first set of bond pads; and   a second plurality of bond wires electrically connecting the upper sub-stack of memory dies to the second set of bond pads,   wherein the bottom sub-stack of memory dies are not electrically connected to the second set of bond pads and the top sub-stack of memory dies are not electrically connected to the first set of bond pads.   
     
     
         14 . The semiconductor memory package of  claim 13 ,
 wherein the first set of bond pads are positioned on the substrate between the stack of staggered memory dies and the interposer.   
     
     
         15 . The semiconductor memory package of  claim 13 , wherein the top surface of the interposer is offset from the top surface of the substrate by a height of at least 50 microns as measured in a direction generally perpendicular to the top surface of the substrate. 
     
     
         16 . The semiconductor device package of  claim 13 , wherein the top surface of the interposer is positioned between the top surface of the substrate and a top surface of an uppermost memory die included in the stack of staggered memory dies. 
     
     
         17 . The semiconductor memory package of  claim 13 , wherein each memory die included in the stack of staggered memory dies has a set of die bond pads, wherein the die bond pads of the first sub-stack of memory dies are electrically connected to the first set of bond pads by the first plurality of bond wires, and the die bond pads of the second sub-stack of memory dies are electrically connected to the second set of bond pads by the second plurality of bond wires. 
     
     
         18 . The semiconductor memory package of  claim 13  further comprising:
 one or more solder balls physically coupling the interposer to the substrate, wherein the one or more solder balls are electrically connected to the substrate; and 
 a through-device via extending through the interposer and electrically connecting the second set of bond pads to the one or more solder balls. 
 
     
     
         19 . The semiconductor memory package of  claim 13  further comprising:
 a third set of bond pads exposed at the top surface of the substrate, the interposer is positioned between the first and third sets of bond pads; and 
 a third plurality of bond wires electrically connected to the second plurality of bond wires and the third set of bond pads, 
 wherein the interposer is mounted directly on the substrate. 
 
     
     
         20 . A semiconductor device package comprising:
 a substrate means for providing electrical interconnections between electrical components coupled to the substrate means, the substrate means including a first set of electrical contact means for transmitting and receiving a plurality of electrical signals;   a stack of storage means each for storing an amount of data, the stack of storage means including a first sub-stack of storage means and a second sub-stack of storage means positioned above the first sub-stack of storage means;   an interposer means for conveying electrical signals between the second sub-stack of storage means and the substrate means, the interposer means positioned on the substrate means and spaced from the stack of storage means;   a second set of electrical contact means for transmitting and receiving a plurality of electrical signals, the second set of electrical contact means being positioned on the interposer means and separated from the substrate means by a height of the interposer means;   a first set of electrical connection means for electrically connecting the first sub-stack of storage means to the first set of electrical contact means, the first set of electrical connection means electrically connected to the first sub-stack of storage means and to the first set of electrical contact means; and   a second set of electrical connection means for electrically connecting the second sub-stack of storage means to the second set of electrical contact means, the second set of electrical connection means electrically connected to the second sub-stack of storage means and to the second set of electrical contact means,   wherein the first sub-stack of storage means and the second sub-stack of storage means are electrically isolated from one another.