Ray tracing hardware acceleration with alternative world space transforms

Abstract

Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.

1 . A ray tracing acceleration hardware device configured to be connected to a processor, the ray tracing acceleration hardware device comprising:
 at least one state storage configured to store a traversal state of an acceleration structure and a ray; and   circuitry configured to, using the ray, traverse a traversal path in the acceleration structure from a root node in a first world space to a leaf node in an object space, and during the traversing, update the stored traversal state upon transforming the ray from a first world space to a second world space and from the second world space to the object space.   
     
     
         2 . The ray tracing acceleration hardware device according to  claim 1 , wherein the update the stored traversal state upon transforming the ray from the first world space to a second world space is performed in response to a first transform node in the traversal path, and the update the stored traversal state upon transforming the ray from the second world space to the object space in response to a second transform node in the traversal path. 
     
     
         3 . The ray tracing acceleration hardware device according to  claim 2 , wherein the first node transform node is an instance node that specifies a first transform from the first world space to the second world space and the second transform node is an instance node that specifies a second transform from the second world space to the object space, and wherein the traversing includes transforming the ray according to the first transform and the second transform at respective nodes in the acceleration structure. 
     
     
         4 . The ray tracing acceleration hardware device according to  claim 1 , wherein the transforming the ray from the first world space to the second world space is in accordance with information stored in the acceleration structure. 
     
     
         5 . The ray tracing acceleration hardware device according to  claim 1 , wherein the circuitry is further configured to test the ray, in the object space, for intersection with bounding volumes defined by the acceleration structure. 
     
     
         6 . The ray tracing acceleration hardware device according to  claim 1 , wherein, before the update, the at least one state is initialized based on information received from the processor relating to the ray, defined in the first world space, and the acceleration structure. 
     
     
         7 . The ray tracing acceleration hardware device according to  claim 1 , wherein the traversal circuitry receives the ray and information of the acceleration structure from the processor, wherein the acceleration data structure comprises hierarchically arranged nodes defining plural bounding volumes bounding objects in a scene, and wherein the first world space is a coordinate space defined for an application running on the processor, and the object space is a coordinate space in which one of more of the objects in the scene are defined. 
     
     
         8 . The ray tracing acceleration hardware device according to  claim 1 , wherein the ray tracing acceleration hardware device is a coprocessor to the processor. 
     
     
         9 . The ray tracing acceleration hardware device according to  claim 1 , wherein the circuitry is further configured to maintain the traversal state as a top level traversal state and top level ray state for traversing the acceleration structure in the first and second world spaces, and to maintain a bottom level traversal state and bottom level ray state for traversing the acceleration structure in the object space, and wherein the circuitry is further configured to store information about the transformed ray in the top level ray state or the bottom level ray state. 
     
     
         10 . The ray tracing acceleration hardware device according to  claim 1 , configured to, in response to reaching a node of an instance node type in the acceleration data structure during the traversing, send information about a state of a continued traversing to a processor. 
     
     
         11 . The ray tracing acceleration hardware device according to  claim 1 , wherein the circuitry is part of a server or a data center employed in generating an image, and the image is streamed to a user device. 
     
     
         12 . The ray tracing acceleration hardware device according to  claim 1 , wherein the circuitry is employed in generating an image, and the image is used for training, testing, or certifying a neural network employed in a machine, robot, or autonomous vehicle. 
     
     
         13 . A system comprising a processor, a parallel processing unit (PPU) and a traversal coprocessor coupled to a memory, wherein the traversal coprocessor comprises:
 at least one state storage configured to store a traversal state of an acceleration structure and a ray; and   circuitry configured to, using the ray, traverse a traversal path in the acceleration structure from a root node in a first world space to a leaf node in an object space, and during the traversing, update the stored state upon transforming the ray from a first world space to a second world space and from the second world space to the object space.   
     
     
         14 . The system according to  claim 13 , wherein the memory is configured to store the acceleration structure of hierarchically-arranged nodes, the hierarchically-arranged nodes defining a plurality of bounding volumes bounding portions of a scene and being axis-aligned in a first coordinate space, and including a plurality of leaf nodes corresponding to surfaces in the scene, the surfaces being in respective object coordinate spaces. 
     
     
         15 . The system according to  claim 14 , wherein the processor is configured to:
 access the acceleration structure in the memory; and   for each of a plurality of frames containing the scene:   select an alternate world space for the scene; and   when the selected world space is different from the first world space, rebuild the acceleration structure in the selected world space and including, for a top level node of the acceleration structure, a transform from the first coordinate space to the selected world space.   
     
     
         16 . The system according to  claim 15 , wherein the PPU is configured to, for each of said plurality of frames containing the scene;
 access the rebuilt acceleration structure; and   in response to detecting the transform for the top level node, transmit information about the ray in the first world space, the rebuilt acceleration structure, and information about the transform to the traversal coprocessor;   receive intersection information for the ray and the rebuilt acceleration structure from the traversal coprocessor; and   render the scene in the frame in accordance with the received intersection information; and   wherein the traversal coprocessor is further configured to:   receive said information about the ray, the rebuilt acceleration structure, and information about the transform, wherein the transforming the ray from the first world space to the second world space is in accordance with the received information about the transform; and   provide the determined one or more intersections to the PPU.   
     
     
         17 . A method of testing, in a hardware device configured to accelerate traversal of an acceleration structure, whether a ray intersects a primitive, comprising:
 initializing a traversal state stored in the hardware device based on information received from a processor connected to the hardware device, the information comprising an acceleration structure and a ray in a first world space; and   traversing, with the ray and by circuitry in the hardware device, a traversal path in the acceleration structure from a root node in the first world space to a leaf node in an object space, and during the traversing, updating the stored state upon transforming the ray from a first world space to a second world space and from the second world space to the object space.