US2024297190A1PendingUtilityA1

Image sensor

Assignee: POWERTECH TECHNOLOGY INCPriority: Mar 1, 2023Filed: Oct 13, 2023Published: Sep 5, 2024
Est. expiryMar 1, 2043(~16.5 yrs left)· nominal 20-yr term from priority
Inventors:Ching-Chao Lin
H10F 39/811H10F 39/804H01L 27/14636H01L 27/14618
40
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An image sensor includes an image sensing chip, an encapsulant, a plurality of outer-side encapsulant vias, an interior wire redistribution layer and an exterior wire redistribution layer. The encapsulant wraps around the image sensing chip, the outer-side encapsulant vias penetrate the encapsulant, and the interior wire redistribution layer is formed on a top surface of the encapsulant, wherein the image sensing chip is electrically connected to the exterior wire redistribution layer through the interior wire redistribution layer and the outer-side encapsulant vias, and then further through the conducting terminals on the exterior wire redistribution layer to connect to the outside. The exterior wire redistribution layer is directly formed underneath the image sensing chip without using a substrate. Since the electrical connection is realized through the outer-side encapsulant vias, the thicknesses of the encapsulant and the size of the packaged image sensor can be reduced.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An image sensor comprising:
 an image sensing chip, including an active surface and a back surface facing each other, and the active surface having an image sensing region, and a plurality of contact pads located on a periphery of the image sensing region on the active surface;   an encapsulant, wrapping around the periphery of the image sensing chip without covering the image sensing region to expose the image sensing region;   a plurality of outer-side encapsulant vias, which penetrates the encapsulant and is located on the outer periphery of the image sensing chip, and an inner wall of each of the plurality of outer-side encapsulant vias has a conducting layer;   an interior wire redistribution layer covering a top surface of the encapsulant and electrically connecting the plurality of contact pads and the conducting layer of the plurality of outer-side encapsulant vias;   a dielectric layer covering the surface of the interior wire redistribution layer and the top surface of the encapsulant;   a transparent cover plate, attached to the top surface of the encapsulant through an adhesive layer, and separated from the image sensing region by a gap;   an exterior wire redistribution layer formed underneath the image sensing chip and a bottom surface of the encapsulant, and the exterior wire redistribution layer electrically connected to the conducting layer of the plurality of outer-side encapsulant vias; and   a plurality of conducting terminals, electrically connected to the exterior wire redistribution layer.   
     
     
         2 . The image sensor as claimed in  claim 1 , wherein the top surface of the encapsulant is flush with the active surface of the image sensing chip. 
     
     
         3 . The image sensor as claimed in  claim 1 , wherein the encapsulant further wraps the back surface of the image sensing chip, and the exterior wire redistribution layer is formed entirely on the bottom surface of the encapsulant. 
     
     
         4 . The image sensor as claimed in  claim 1 , wherein the height of the gap is equal to the thickness of the dielectric layer. 
     
     
         5 . The image sensor as claimed in  claim 1 , wherein the interior wire redistribution layer extends horizontally to the active surface to electrically connect the plurality of contact pads; the dielectric layer directly covers a periphery of the active surface. 
     
     
         6 . The image sensor as claimed in  claim 1 , wherein an aperture of each of the plurality of outer-side encapsulant vias is tapered from the bottom surface to the top surface of the encapsulant; the conducting layer is filled into the plurality of outer-side encapsulant vias. 
     
     
         7 . The image sensor as claimed in  claim 1 , wherein, the back surface of the image sensing chip is exposed without being covered by the encapsulant; the encapsulant further covers the plurality of contact pads on the active surface;
 the encapsulant further includes a plurality of inner-side encapsulant vias; each of the plurality of inner-side encapsulant vias penetrates the encapsulant located on the image sensing chip, and each of the plurality of contact pads is respectively exposed at one end of a corresponding inner-side encapsulant via of the plurality of inner-side encapsulant vias;   an inner wall of each of the plurality of inner-side encapsulant vias has a conducting layer which is electrically connected to the inner wire redistribution layer and a contact pad of the plurality of contact pads.   
     
     
         8 . The image sensor as claimed in  claim 1 , wherein the dielectric layer is filled into each of the plurality of inner-side encapsulant vias and each of the plurality of outer-side encapsulant vias;
 the exterior wire redistribution layer is formed on the bottom surface of the encapsulant and the back surface of the image sensing chip.   
     
     
         9 . The image sensor as claimed in  claim 1 , wherein the encapsulant on the active surface has a sidewall facing the image sensing region, and the sidewall is vertically flush with a surface of the dielectric layer, and the active surface is directly exposed without being covered by the encapsulant. 
     
     
         10 . The image sensor as claimed in  claim 1 , wherein the apertures of each of the plurality of inner-side encapsulant vias and each of the plurality of outer-side encapsulant vias are tapered from the top surface toward the bottom surface of the encapsulant.

Join the waitlist — get patent alerts

Track US2024297190A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.