Layout method, non-transitory computer-readable medium, and associated integrated circuit

Abstract

A layout method, a non-transitory computer-readable medium, and an associated integrated circuit are provided. The non-transitory computer-readable medium records a software program for performing the layout method of the integrated circuit having Q circuit blocks. The layout method includes the following steps. K gate-controlled elements and (K−1) buffers are placed on the edge of a qth circuit block. The K gate-controlled elements are connected between a supply voltage terminal and the qth circuit block. (K−1) gate-controlled elements, including an SEL[1]-th gate-controlled element, are selected as (K−1) source nodes. Another (K−1) gate-controlled elements, other than the SEL[1]-th gate-controlled element, are selected as (K−1) destination nodes. The (K−1) buffers are routed as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes.

What is claimed is: 
     
         1 . A layout method used with an integrated circuit comprising Q circuit blocks, wherein the layout method comprises steps of:
 placing K gate-controlled elements and (K−1) buffers on an edge of a qth circuit block among the Q circuit blocks, wherein each of the K gate-controlled elements comprises a first terminal, a second terminal, and a control terminal, and each of the (K−1) buffers comprises an input terminal and an output terminal;   connecting the first terminals of the K gate-controlled elements to a supply voltage terminal;   connecting the second terminals of the K gate-controlled elements to the qth circuit block;   selecting, among the K gate-controlled elements, (K−1) gate-controlled elements comprising an SEL[1]-th gate-controlled element as (K−1) source nodes, wherein the control terminal of the SEL[1]-th gate-controlled element receives a qth enabling signal corresponding to the qth circuit block;   selecting, among the K gate-controlled elements, another (K−1) gate-controlled elements other than the SEL[1]-th gate-controlled element as (K−1) destination nodes; and   routing the (K−1) buffers as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes, respectively,   wherein Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q.   
     
     
         2 . The layout method according to  claim 1 , wherein the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting the SEL[1]-th gate-controlled element as a first source node among the (K−1) source nodes; 
 selecting an (SEL[1]+X)-th gate-controlled element among the K gate-controlled elements as a first destination node among the (K−1) destination nodes; and 
 placing a first buffer among the (K−1) buffers as a first delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the SEL[1]-th gate-controlled element is connected to the input terminal of the first buffer, and the output terminal of the first buffer is connected to the control terminal of the (SEL[1]+X)-th gate-controlled element. 
 
     
     
         3 . The layout method according to  claim 2 , wherein when the SEL[1]-th gate-controlled element is switched on in response to the qth enabling signal, the SEL[1]-th gate-controlled element conducts a voltage at the supply voltage terminal to the qth circuit block, and the first delayed gating line conducts the qth enabling signal with a delay to the control terminal of the (SEL[1]+X)-th gate-controlled element to make the (SEL[1]+X)-th gate-controlled element switched on in response to the qth enabling signal with the delay conducted through the first delayed gating line. 
     
     
         4 . The layout method according to  claim 2 , wherein the first delayed gating line is longer in length if X has a greater value. 
     
     
         5 . The layout method according to  claim 2 , wherein the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting the (SEL[1]+X)-th gate-controlled element as a second source node among the (K−1) source nodes; 
 selecting an (SEL[1]+2*X)-th gate-controlled element among the K gate-controlled elements as a second destination node among the (K−1) destination nodes; and 
 placing a second buffer among the (K−1) buffers as a second delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the (SEL[1]+X)-th gate-controlled element is connected to the input terminal of the second buffer, and the output terminal of the second buffer is connected to the control terminal of the (SEL[1]+2*X)-th gate-controlled element. 
 
     
     
         6 . The layout method according to  claim 1 , wherein the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting an SEL[2]-th gate-controlled element among the K gate-controlled elements as a (Y+1)-th source node among the (K−1) source nodes, wherein SEL[2] is a positive integer not equivalent to SEL[1]; 
 selecting an (SEL[2]+X)-th gate-controlled element among the K gate-controlled elements as a (Y+1)-th destination node among the (K−1) destination nodes; and 
 placing a (Y+1)-th buffer among the (K−1) buffers as a (Y+1)th delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the SEL[2]-th gate-controlled element is connected to the input terminal of the (Y+1)-th buffer, and the output terminal of the (Y+1)-th buffer is connected to the control terminal of the (SEL[2]+X)-th gate-controlled element. 
 
     
     
         7 . The layout method according to  claim 6 , wherein SEL[2] is greater than (SEL[1]−X), and SEL[2] is smaller than (SEL[1]+X). 
     
     
         8 . The layout method according to  claim 7 , wherein if SEL[1] is equivalent to  1 , SEL[2] is greater than SEL[1]. 
     
     
         9 . The layout method according to  claim 1 , wherein the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting an (SEL[1]+X*(Y−1))-th gate-controlled element among the K gate-controlled elements as a Yth source node among the (K−1) source nodes; 
 selecting an SEL[2]-th gate-controlled element among the K gate-controlled elements as a Yth destination node among the (K−1) destination nodes; and 
 placing a Yth buffer among the (K−1) buffers as a Yth delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the (SEL[1]+X*(Y−1))-th gate-controlled element is connected to the input terminal of the Yth buffer, and the output terminal of the Yth buffer is connected to the control terminal of the SEL[2]-th gate-controlled element. 
 
     
     
         10 . The layout method according to  claim 9 , wherein (SEL[1]+X*Y) is smaller than or equivalent to K, and (SEL[1]+X*(Y+1)) is greater than K. 
     
     
         11 . The layout method according to  claim 10 , wherein if (SEL[1]+X*Y) is smaller than K, the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting a (K−1)-th gate-controlled element among the K gate-controlled elements as a (K−SEL[1])-th source node among the (K−1) source nodes; 
 selecting a Kth gate-controlled element among the K gate-controlled elements as a (K−SEL[1])-th destination node among the (K−1) destination nodes; and 
 placing a (K−SEL[1])-th buffer among the (K−1) buffers as a (K−SEL[1])-th delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the (K−1)-th gate-controlled element is connected to the input terminal of the (K−SEL[1])-th buffer, and the output terminal of the (K−SEL[1])-th buffer is connected to the control terminal of the Kth gate-controlled element. 
 
     
     
         12 . The layout method according to  claim 1 , further comprising steps of:
 selecting a first selected gate-controlled element among the (K−1) gate-controlled elements as an (X*Y−1)-th destination node among the (K−1) destination nodes and an (X*Y)-th source node among the (K−1) source nodes;   selecting a second selected gate-controlled element among the (K−1) gate-controlled elements as an (X*Y−1)-th source node among the (K−1) source nodes;   selecting a third selected gate-controlled element among the (K−1) gate-controlled elements as an (X*Y)-th destination node among the (K−1) destination nodes, wherein   a distance between the first selected gate-controlled element and the second selected gate-controlled element is X gate-controlled elements, and a distance between the first selected gate-controlled element and the third selected gate-controlled element is smaller than X gate-controlled elements.   
     
     
         13 . The layout method according to  claim 1 , wherein the K gate-controlled elements are divided into Y routing sections, and each of the Y routing sections corresponds to X gate-controlled elements among the K gate-controlled elements. 
     
     
         14 . The layout method according to  claim 13 , wherein a first routing section among the Y routing sections corresponds to the X gate-controlled elements starting from an INIT-th gate-controlled element to a (INIT+X−1)-th gate-controlled element. 
     
     
         15 . The layout method according to  claim 14 , wherein if INIT is greater than 1, the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting a Kth gate-controlled element among the K gate-controlled elements as a (K−INIT+1)-th source node among the (K−1) source nodes; 
 selecting a first gate-controlled element among the K gate-controlled elements as a (K−INIT+1)-th destination node among the (K−1) destination nodes; and 
 placing a (K−INIT+1)-th buffer among the (K−1) buffers as a (K−INIT+1)-th delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the Kth gate-controlled element is connected to the input terminal of the (K−INIT+1)-th buffer, and the output terminal of the (K−INIT+1)-th buffer is connected to the control terminal of the first gate-controlled element. 
 
     
     
         16 . The layout method according to  claim 15 , wherein if INIT is greater than 2, the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes comprises steps of:
 selecting the first gate-controlled element as a (K−INIT+2)-th source node among the (K−1) source nodes; 
 selecting a second gate-controlled element among the K gate-controlled elements as a (K−INIT+2)-th destination node among the (K−1) destination nodes; and 
 placing a (K−INIT+2)-th buffer among the (K−1) buffers as a (K−INIT+2)-th delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the first gate-controlled element is connected to the input terminal of the (K−INIT+2)-th buffer, and the output terminal of the (K−INIT+2)-th buffer is connected to the control terminal of the second gate-controlled element. 
 
     
     
         17 . The layout method according to  claim 14 , wherein if INIT is greater than 2, the step of routing the (K−1) buffers as the (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes further comprises steps of:
 selecting an (INIT−2)-th gate-controlled element among the K gate-controlled elements as a (K−1)-th source node among the (K−1) source nodes; 
 selecting an (INIT−1)-th gate-controlled element among the K gate-controlled elements as a (K−1)-th destination node among the (K−1) destination nodes; and 
 placing a (K−1)-th buffer among the (K−1) buffers as a (K−1)-th delayed gating line among the (K−1) delayed gating lines, wherein 
 the control terminal of the (INIT−2)-th gate-controlled element is connected to the input terminal of the (K−1)-th buffer, and the output terminal of the (K−1)-th buffer is connected to the control terminal of the (INIT−1)-th gate-controlled element. 
 
     
     
         18 . The layout method according to  claim 14 , wherein SEL[1] is greater than or equivalent to INIT, and SEL[1] is smaller than or equivalent to (INIT+X−1). 
     
     
         19 . A non-transitory computer-readable medium recording a software program for performing a layout method of an integrated circuit, the layout method comprising steps of:
 placing K gate-controlled elements and (K−1) buffers on an edge of a qth circuit block among Q circuit blocks in the integrated circuit, wherein each of the K gate-controlled elements comprises a first terminal, a second terminal, and a control terminal, and each of the (K−1) buffers comprises an input terminal and an output terminal;   connecting the first terminals of the K gate-controlled elements to a supply voltage terminal;   connecting the second terminals of the K gate-controlled elements to the qth circuit block;   selecting, among the K gate-controlled elements, (K−1) gate-controlled elements comprising an SEL[1]-th gate-controlled element as (K−1) source nodes, wherein the control terminal of the SEL[1]-th gate-controlled element receives a qth enabling signal corresponding to the qth circuit block;   selecting, among the K gate-controlled elements, another (K−1) gate-controlled elements other than the SEL[1]-th gate-controlled element as (K−1) destination nodes; and   routing the (K−1) buffers as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes, respectively, wherein Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q.   
     
     
         20 . An integrated circuit, comprising:
 Q layout blocks corresponding to Q supply voltages, respectively, a qth layout block among the Q layout blocks comprising:
 a qth circuit block operating with a qth supply voltage among the Q supply voltages; 
 K gate-controlled elements placed on an edge of the qth circuit block, wherein each of the K gate-controlled elements comprises a first terminal connected to a supply voltage terminal, a second terminal connected to the qth circuit block, and a control terminal, and the control terminal of an SEL[1]-th gate-controlled element among the K gate-controlled elements receives a qth enabling signal corresponding to the qth circuit block; and 
 (K−1) buffers placed on the edge of the qth circuit block, wherein each of the (K−1) buffers comprises an input terminal and an output terminal, wherein 
 (K−1) gate-controlled elements, among the K gate-controlled elements, comprising the SEL[1]-th gate-controlled element are selected as (K−1) source nodes, and 
 another (K−1) gate-controlled elements, among the K gate-controlled elements, other than the SEL[1]-th gate-controlled element are selected as (K−1) destination nodes, 
 wherein the (K−1) buffers are routed as (K−1) delayed gating lines connected between the (K−1) source nodes and the (K−1) destination nodes, respectively, 
 wherein Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q.