Memory semiconductor device and fabrication method thereof

Abstract

A method includes forming storage channel structures including a functional layer, a channel layer, a filling layer and a slit in the filling layer, thinning a first substrate to form a second substrate, removing a second bottom section outside the second substrate to expose a first bottom section slit, filling a dielectric material layer in the first bottom section slit, removing the second substrate and a first bottom section functional layer to form a first dielectric section filled in the first bottom section slit and expose a first bottom section channel layer, forming a common source layer contacting the first bottom section channel layer, the first bottom section filling layer and the first dielectric section. After inverting the stack structure, the substrate is thinned, and the exposed functional layer and the channel layer are removed.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor device, comprising:
 forming a stack structure comprising gate conductive layers and interlayer insulating layers alternatively stacked on a first lateral surface of a first substrate and storage channel structures extending in the stack structure and into the first substrate in a longitudinal direction perpendicular to the first lateral surface, the storage channel structures having a functional layer, a channel layer, a filling layer and a slit in the filling layer;   thinning the first substrate from a side of the first substrate away from the first lateral surface to form a second substrate and expose a first channel structure of the storage channel structures, the first channel structure comprising a second bottom section exposed from the second substrate and a first bottom section in the second substrate, the first bottom section comprising a first bottom section channel layer, a first bottom section functional layer, a first bottom section filling layer and a first bottom section slit;   removing the second bottom section and exposing the first bottom section slit at the first bottom section;   filling a dielectric material layer in the first bottom section slit;   removing the second substrate and the first bottom section functional layer at the first bottom section to form a first dielectric section filled in the first bottom section slit and expose the first bottom section channel layer of the first bottom section; and   forming a common source layer contacting the first bottom section channel layer, the first bottom section filling layer and the first dielectric section.   
     
     
         2 . The method of  claim 1 , wherein the second bottom section comprises a second bottom section channel layer, a second bottom section filling layer on an inner side of the second bottom section channel layer, and a second bottom section functional layer on an outer side of the second bottom section channel layer;
 wherein the step of removing the second bottom section comprises:
 removing the second bottom section functional layer on the outer side of the second bottom section channel layer of the second bottom section to expose the second bottom section channel layer of the second bottom section; 
 removing the second bottom section channel layer at the second bottom section to expose the second bottom section filling layer on the inner side of the second bottom section channel layer of the second bottom section; and 
 removing the second bottom section filling layer. 
   
     
     
         3 . The method of  claim 2 , wherein the step of removing the second bottom section filling layer on the inner side of the second bottom section channel layer of the second bottom section comprises:
 removing the second bottom section filling layer on the inner side of the second bottom section channel layer of the second bottom section and thinning the first bottom section functional layer on the outer side of the first bottom section channel layer of the first bottom section to form a first recess;   wherein the step of filling the dielectric material layer in the first bottom section slit comprises:
 forming a dielectric material layer on the second substrate to fill the dielectric material layer in the first bottom section slit and the first recess; 
   wherein the step of forming the first dielectric section filled in the first bottom section slit comprises:
 removing the dielectric material layer outside the first bottom section slit to form the first dielectric section filled in the first bottom section slit. 
   
     
     
         4 . The method of  claim 3 , wherein the step of removing the dielectric material layer outside the first bottom section slit comprises:
 removing the dielectric material layer on the second substrate; and   removing the dielectric material layer in the first recess and thinning the dielectric material layer in the first bottom section slit to form the first dielectric section filled in the first bottom section slit.   
     
     
         5 . The method of  claim 4 , wherein the step of forming the dielectric material layer on the second substrate to fill the dielectric material layer in the first bottom section slit and the first recess comprises:
 forming the dielectric material layer on the second substrate to fill the dielectric material layer in the first bottom section slit and the first recess to form a second dielectric section in the first recess;   wherein the step of removing the dielectric material layer in the first recess comprises:
 removing the second dielectric section; 
   wherein the step of removing the second substrate is between the step of removing the dielectric material layer on the second substrate and the step of removing the second dielectric section.   
     
     
         6 . The method of  claim 5 , wherein the step of removing the first bottom section functional layer at the first bottom section comprises:
 removing the first bottom section functional layer at the first bottom section, removing the second dielectric section, thinning the first bottom section filling layer at the first bottom section and thinning the dielectric material layer in the first bottom section slit.   
     
     
         7 . The method of  claim 1 , wherein the first bottom section functional layer comprises a first oxide layer, a first nitride layer and a second oxide layer, wherein the first nitride layer is between the first oxide layer and the second oxide layer, and the first oxide layer is on a side of the first nitride layer away from the first bottom section channel layer;
 wherein the step of removing the first bottom section functional layer at the first bottom section comprises:
 removing the first oxide layer, removing the first nitride layer and removing the second oxide layer. 
   
     
     
         8 . The method of  claim 7 , wherein the stack structure further comprises a termination layer between the first substrate and the gate conductive layer and the interlayer insulating layer;
 wherein the semiconductor device further comprises a first insulating layer on a side of the termination layer away from the gate conductive layer;   wherein the step of removing the first oxide layer comprises:
 removing the first oxide layer and removing the first insulating layer. 
   
     
     
         9 . A semiconductor device, comprising:
 a stack structure comprising gate conductive layers and interlayer insulating layers alternatively stacked in a longitudinal direction and storage channel structures penetrating the stack structure in the longitudinal direction, the storage channel structures having a bottom section protruding from a first side of the stack structure; and   a common source layer located on the first side of the stack structure;   wherein the storage channel structures comprise a first channel structure having a first bottom section, the first bottom section comprises a first bottom section channel layer, a first bottom section filling layer and a first dielectric section on an inner side of the first bottom section channel layer, and the common source layer is disposed to contact the first bottom section channel layer, the first bottom section filling layer and the first dielectric section.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the first bottom section further comprises a first bottom section slit sealed by the first bottom section filling layer and the first dielectric section. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the storage channel structures further comprise a second channel structure having a third bottom section, and the third bottom section comprises a third bottom section channel layer and a third bottom section filling layer on an inner side of the third bottom section channel layer;
 wherein the common source layer is disposed to contact the third bottom section channel layer.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the third bottom section further comprises a third bottom section slit located in and sealed by the third bottom section filling layer. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the third bottom section channel layer at the third bottom section has a height in the longitudinal direction smaller than that of the first bottom section channel layer at the first bottom section in the longitudinal direction. 
     
     
         14 . The semiconductor device of  claim 9 , wherein the first bottom section channel layer at the first bottom section has a height in the longitudinal direction greater than that of the first bottom section filling layer at the first bottom section in the longitudinal direction. 
     
     
         15 . The semiconductor device of  claim 14 , wherein a difference between the height of the first bottom section channel layer at the first bottom section in the longitudinal direction and the height of the first bottom section filling layer at the first bottom section in the longitudinal direction is 15 nm to 2 μm. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the first bottom section channel layer and the first bottom section filling layer at the first bottom section and the first dielectric section form a first groove in which the common source layer is disposed. 
     
     
         17 . The semiconductor device of  claim 9 , wherein the first bottom section channel layers of any two of the first bottom sections have equal heights in the longitudinal direction. 
     
     
         18 . The semiconductor device of  claim 9 , wherein the semiconductor device further comprises:
 a gate line slit structure penetrating the stack structure in the longitudinal direction and having a slit filler bottom section protruding from the first side of the stack structure.   
     
     
         19 . The semiconductor device of  claim 9 , wherein the materials of the first bottom section filling layer and the first dielectric section are the same. 
     
     
         20 . A memory system, comprising:
 a memory; and   a controller coupled to the memory and configured to control the memory to store data;   wherein the memory comprises:
 a stack structure comprising gate conductive layers and interlayer insulating layers alternatively stacked in a longitudinal direction and storage channel structures penetrating the stack structure in the longitudinal direction, the storage channel structures having a bottom section protruding from a first side of the stack structure; and 
 a common source layer located on the first side of the stack structure; 
   wherein the storage channel structures comprise a first channel structure having a first bottom section, the first bottom section comprises a first bottom section channel layer, a first bottom section filling layer and a first dielectric section on an inner side of the first bottom section channel layer, and the common source layer is disposed to contact the first bottom section channel layer, the first bottom section filling layer and the first dielectric section.