Cfet with via fuse structure and method

Abstract

An embodiment includes a method including forming a first conductive feature and a second conductive feature in a substrate. The method also includes forming a first complementary field-effect transistor (CFET) over the substrate, the forming including forming a first lower transistor including a first gate and a first source/drain region. The method also includes forming a first upper transistor including a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor. The method also includes forming a conductive via fuse connected to the first conductive feature and the second source/drain region.

What is claimed is: 
     
         1 . A method comprising:
 forming a first conductive feature and a second conductive feature in a substrate;   forming a first complementary Field-Effect Transistor (CFET) over the substrate, the forming comprising:
 forming a first lower transistor comprising a first gate and a first source/drain region; and 
 forming a first upper transistor comprising a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor; and 
   forming a conductive via fuse connected to the first conductive feature and the second source/drain region.   
     
     
         2 . The method of  claim 1 , wherein the conductive via fuse is adjacent the first lower transistor. 
     
     
         3 . The method of  claim 1 , wherein the first and second conductive features are buried power rails. 
     
     
         4 . The method of  claim 1 , wherein the first conductive feature is a bit line of a memory cell array. 
     
     
         5 . The method of  claim 1  further comprising:
 forming a conductive via connected to the second conductive feature and the first source/drain region. 
 
     
     
         6 . The method of  claim 5 , wherein the conductive via fuse is longer than the conductive via. 
     
     
         7 . The method of  claim 5 , wherein the first lower transistor is not part of active circuitry and the first gate, the first source/drain region, and the second conductive feature are all coupled to a power supply voltage V DD . 
     
     
         8 . The method of  claim 1 , wherein the conductive via fuse is configured to function as a fuse for the CFET. 
     
     
         9 . The method of  claim 1 , wherein the first lower transistor and the first upper transistor are formed by processes comprising:
 forming the first lower transistor in a first wafer;   forming the first upper transistor in a second wafer; and   bonding the first wafer to the second wafer.   
     
     
         10 . The method of  claim 1 , wherein the first upper transistor is formed after the first lower transistor has been formed. 
     
     
         11 . A structure comprising:
 a first conductive feature and a second conductive feature in a substrate;   a first complementary Field-Effect Transistor (CFET) over the substrate, the CFET comprising:
 a first lower transistor comprising a first gate and a first source/drain region; and 
 a first upper transistor comprising a second gate, a second source/drain region, and a first contact structure on the second source/drain region, the first upper transistor overlapping the first lower transistor; and 
   a conductive via fuse connected to the first contact structure and the first conductive feature.   
     
     
         12 . The structure of  claim 11 , wherein the first and second conductive features are buried power rails in the substrate. 
     
     
         13 . The structure of  claim 12 , wherein the first conductive feature is a bit line of a memory cell array. 
     
     
         14 . The structure of  claim 11  further comprising:
 a second contact structure on and connected to the first source/drain region; and 
 a conductive via connected to the second contact structure and the first source/drain region, the conductive via fuse being longer than the conductive via. 
 
     
     
         15 . The structure of  claim 14  further comprising:
 a first interlayer dielectric over the second conductive feature and the first source/drain region, the conductive via fuse extending through the first interlayer dielectric. 
 
     
     
         16 . The structure of  claim 14 , wherein the first lower transistor is not part of active circuitry and the first gate, the first source/drain region, and the second conductive feature are all coupled to a power supply voltage V DD . 
     
     
         17 . The structure of  claim 11 , wherein the conductive via fuse is configured to function as a fuse for the CFET. 
     
     
         18 . A structure comprising:
 a complementary Field-Effect Transistor (CFET) comprising:
 a first buried conductive feature and a second buried conductive feature in a substrate; 
 a lower transistor comprising:
 a first gate stack; 
 a first source/drain region; 
 a first contact structure on and connected to the first source/drain region; and 
 a first conductive via connecting the first contact structure and the first buried conductive feature; and 
 
 an upper transistor overlapping the lower transistor and comprising:
 a second gate stack; and 
 a second source/drain region; 
 a second contact structure on and connected to the second source/drain region; and 
 a second conductive via connecting the second contact structure and the second buried conductive feature. 
 
   
     
     
         19 . The structure of  claim 18 , wherein the second conductive via is configured to function as a fuse for the CFET. 
     
     
         20 . The structure of  claim 18 , wherein the second conductive via is longer than the first conductive via.