Electronic device and power switching control method

Abstract

An electronic device and a power switching control method are provided. The electronic device includes a basic input/output system (BIOS), an embedded controller, and a control chip. The BIOS is configured to generate a first handshake command when executing an update mode. The embedded controller is coupled to the BIOS and includes a general-purpose input-output (GPIO) pin. The embedded controller performs a handshake procedure with the BIOS according to the first handshake command, and determines a voltage level of the GPIO pin according to the first handshake command. The control chip is coupled to the GPIO pin of the embedded controller, and is configured to determine a power switching waiting time of a power switching unit according to the voltage level of the GPIO pin.

What is claimed is: 
     
         1 . An electronic device, comprising:
 a basic input/output system (BIOS), configured to generate a first handshake command when executing an update mode;   an embedded controller, coupled to the BIOS and comprising a general-purpose input-output (GPIO) pin, wherein the embedded controller performs a handshake procedure with the BIOS according to the first handshake command, and determines a voltage level of the GPIO pin according to the first handshake command; and   a control chip, coupled to the GPIO pin of the embedded controller, and configured to determine a power switching waiting time of a power switching unit according to the voltage level of the GPIO pin.   
     
     
         2 . The electronic device according to  claim 1 , wherein the embedded controller transmits back a second handshake command to the BIOS according to the first handshake command, wherein the first handshake command and the second handshake command have a same encoding structure. 
     
     
         3 . The electronic device according to  claim 2 , wherein the first handshake command comprises a plurality of bits for indicating a confirmation time, and when the embedded controller does not receive a next first handshake command within the confirmation time, the embedded controller switches the voltage level of the GPIO pin. 
     
     
         4 . The electronic device according to  claim 3 , wherein the first handshake command further comprises another plurality of bits for indicating whether the embedded controller is operating normally, whether the BIOS is operating normally, and whether the BIOS is executing the update mode. 
     
     
         5 . The electronic device according to  claim 1 , wherein when execution of the update mode ends, the BIOS outputs a third handshake command to the embedded controller, such that the embedded controller ends the handshake procedure according to the third handshake command,
 wherein the first handshake command and the third handshake command have a same encoding structure.   
     
     
         6 . The electronic device according to  claim 1 , wherein when the update mode is executed, the GPIO pin has a first voltage level, such that the control chip sets the power switching waiting time to a first time length, and
 when the update mode is not executed, the GPIO pin has a second voltage level, such that the control chip sets the power switching waiting time to a second time length,   wherein the first time length is greater than the second time length.   
     
     
         7 . The electronic device according to  claim 1 , wherein the control chip comprises:
 a first counting unit, coupled to the power switching unit;   a second counting unit; and   a logic circuit, comprising a first input pin, a second input pin, a third input pin, and an output pin, and is configured to execute a look up table,   wherein the first input pin is coupled to the GPIO pin, the second input pin is coupled to the first counting unit, the third input pin is coupled to the power switching unit, and the output pin is coupled to the second counting unit,   wherein the logic circuit executes the look up table according to a plurality of voltage levels of the first input pin, the second input pin, and the third input pin, to output a control signal to the second counting unit through the output pin according to a look up result, and the second counting unit delays outputting the control signal.   
     
     
         8 . The electronic device according to  claim 7 , wherein when the update mode is executed, the power switching waiting time is equal to a sum of a first delay time of the first counting unit and a second delay time of the second counting unit, and
 wherein when the update mode is not executed, the power switching waiting time is equal to the second delay time.   
     
     
         9 . The electronic device according to  claim 1 , wherein the power switching unit is a power key of the electronic device, and when the power key is pressed continuously for more than the power switching waiting time, the electronic device executes a shutdown procedure. 
     
     
         10 . The electronic device according to  claim 1 , wherein the update mode is the BIOS updating firmware. 
     
     
         11 . A power switching control method, applied to an electronic device, and comprising:
 generating a first handshake command by a basic input/output system (BIOS) when executing an update mode;   performing a handshake procedure with the BIOS by an embedded controller according to the first handshake command, and determining a voltage level of a general-purpose input-output (GPIO) pin according to the first handshake command; and   determining a power switching waiting time of a power switching unit by a control chip according to the voltage level of the GPIO pin.   
     
     
         12 . The power switching control method according to  claim 11 , further comprising:
 transmitting back a second handshake command to the BIOS by the embedded controller according to the first handshake command,   wherein the first handshake command and the second handshake command have a same encoding structure.   
     
     
         13 . The power switching control method according to  claim 11 , wherein the first handshake command comprises a plurality of bits for indicating a confirmation time, and when the embedded controller does not receive a next first handshake command within the confirmation time, the embedded controller switches the voltage level of the GPIO pin. 
     
     
         14 . The power switching control method according to  claim 13 , wherein the first handshake command further comprises another plurality of bits for indicating whether the embedded controller is operating normally, whether the BIOS is operating normally, and whether the BIOS is executing the update mode. 
     
     
         15 . The power switching control method according to  claim 11 , further comprising:
 when execution of the update mode ends, outputting a third handshake command to the embedded controller by the BIOS, such that the embedded controller ends the handshake procedure according to the third handshake command,   wherein the first handshake command and the third handshake command have a same encoding structure.   
     
     
         16 . The power switching control method according to  claim 11 , wherein when the update mode is executed, the GPIO pin has a first voltage level, such that the control chip sets the power switching waiting time to a first time length, and
 when the update mode is not executed, the GPIO pin has a second voltage level, such that the control chip sets the power switching waiting time to a second time length,   wherein the first time length is greater than the second time length.   
     
     
         17 . The power switching control method according to  claim 11 , wherein the control chip comprises a first counting unit coupled to the power switching unit, a second counting unit, and a logic circuit, wherein a first input pin of the logic circuit is coupled to the GPIO pin, a second input pin of the logic circuit is coupled to the first counting unit, a third input pin of the logic circuit is coupled to the power switching unit, and an output pin of the logic circuit is coupled to the second counting unit,
 wherein determining the power switching waiting time of the power switching unit by the control chip according to the voltage level of the GPIO pin comprises:   executing a look up table by the logic circuit according to a plurality of voltage levels of the first input pin, the second input pin, and the third input pin; and   outputting a control signal to the second counting unit by the logic circuit through the output pin according to a look up result, and delaying outputting the control signal by the second counting unit.   
     
     
         18 . The power switching control method according to  claim 17 , wherein when the update mode is executed, the power switching waiting time is equal to a sum of a first delay time of the first counting unit and a second delay time of the second counting unit, and
 wherein when the update mode is not executed, the power switching waiting time is equal to the second delay time.   
     
     
         19 . The power switching control method according to  claim 11 , wherein the power switching unit is a power key of the electronic device, and when the power key is pressed continuously for more than the power switching waiting time, the electronic device executes a shutdown procedure. 
     
     
         20 . The power switching control method according to  claim 11 , wherein the update mode is the BIOS updating firmware.