Reaction tube, semiconductor manufacturing apparatus therewith, and method of manufacturing semiconductor device using the same

Abstract

A semiconductor manufacturing apparatus may include a substrate boat configured to load a plurality of substrates; a process chamber configured to enclose the substrate boat; and a reaction tube between the substrate boat and the process chamber. The reaction tube may include a gas flowing part configured to allow for a flow of a process gas; a process part defining gas slits and an exhausting hole; and baffles on an inner side surface of the process part, excluding the exhausting hole.

What is claimed is: 
     
         1 . A semiconductor manufacturing apparatus, comprising:
 a substrate boat configured to load a plurality of substrates;   a process chamber configured to enclose the substrate boat; and   a reaction tube between the substrate boat and the process chamber,   wherein the reaction tube comprises:
 a gas flowing part configured to allow for a flow of a process gas; 
 a process part defining gas slits and an exhausting hole; and 
 baffles on an inner side surface of the process part, excluding the exhausting hole. 
   
     
     
         2 . The semiconductor manufacturing apparatus of  claim 1 , wherein the baffles have an arc shape when viewed in a plan view. 
     
     
         3 . The semiconductor manufacturing apparatus of  claim 1 , wherein the baffles are spaced apart from each other in a vertical direction. 
     
     
         4 . The semiconductor manufacturing apparatus of  claim 1 , wherein the gas slits are in the process part that is adjacent to the gas flowing part, and
 the exhausting hole is in the process part that is opposite to the gas slits.   
     
     
         5 . The semiconductor manufacturing apparatus of  claim 1 , wherein the gas slits extend in a horizontal direction and are spaced apart from each other in a vertical direction. 
     
     
         6 . The semiconductor manufacturing apparatus of  claim 1 , wherein the baffles are not overlapped with the gas slits in a horizontal direction. 
     
     
         7 . The semiconductor manufacturing apparatus of  claim 1 , wherein the baffles have different widths from each other in a horizontal direction. 
     
     
         8 . The semiconductor manufacturing apparatus of  claim 1 , wherein the process part comprises an upper portion and a side portion that are coupled to each other, and
 the gas slits and the exhausting hole are defined in the side portion.   
     
     
         9 . The semiconductor manufacturing apparatus of  claim 8 , wherein an upper surface of each of the baffles is coplanar with an upper surface of a respective portion of the side portion between the gas slits. 
     
     
         10 . The semiconductor manufacturing apparatus of  claim 8 , wherein a distance in a horizontal direction between an innermost part of the baffles and a center of a process space of the process part is smaller than a distance in the horizontal direction between an innermost part of the side portion and the center of the process part. 
     
     
         11 . The semiconductor manufacturing apparatus of  claim 8 , wherein the baffles and the process part are integrally formed. 
     
     
         12 . The semiconductor manufacturing apparatus of  claim 1 , further comprising an outer tube between the reaction tube and the process chamber. 
     
     
         13 . A reaction tube, comprising:
 a side portion defines gas slits that are spaced apart from each other in a vertical direction, and an exhausting hole, that is opposite to the gas slits;   an upper portion connected to the side portion;   baffles that are on an inner side surface of the side portion, excluding on the exhausting hole, and are spaced apart from each other in the vertical direction; and   a gas flowing part adjacent to the gas slits of the side portion,   wherein upper surfaces of portions of the side portion between the gas slits is at a same level as an upper surface of a respective one of the baffles, and   wherein the baffles have an arc shape when viewed in a plan view.   
     
     
         14 . The reaction tube of  claim 13 , wherein the gas flowing part defines a gas flowing passageway,
 the upper portion and the side portion define a process space, and   the gas flowing passageway is connected to the process space through the gas slits.   
     
     
         15 . The reaction tube of  claim 13 , wherein each of the gas slits extends in a horizontal direction, and
 the exhausting hole extends in the vertical direction.   
     
     
         16 . The reaction tube of  claim 13 , wherein a width of the upper surface of each of the baffles is larger than a width of a lower surface of each of the baffles. 
     
     
         17 . A method of manufacturing a semiconductor device, the method comprising:
 loading substrates on a substrate boat;   placing the substrate boat in a reaction tube after loading the substrates;   performing a semiconductor manufacturing process with respect to the substrates in the reaction tube; and   unloading the substrates after performing the semiconductor manufacturing process,   wherein the reaction tube includes an upper portion, a side portion, and baffles on an inner side surface of the side portion, and   wherein the placing the substrate boat in the reaction tube comprises placing an upper surface of each of the substrates at a same level as an upper surface of a respective one of the baffles.   
     
     
         18 . The method of  claim 17 , wherein the performing the semiconductor manufacturing process comprises supplying, in a horizontal direction, a process gas to a region on the upper surface of each of the substrates. 
     
     
         19 . The method of  claim 17 , wherein the performing the semiconductor manufacturing process comprises rotating the substrate boat in a clockwise or counterclockwise direction. 
     
     
         20 . The method of  claim 17 , wherein the performing the semiconductor manufacturing process comprises forming at least one from among a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer on the substrates.