Cfet cell architecture with a side-routing structure

Abstract

This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

What is claimed is: 
     
         1 . A complementary field effect transistor (CFET) cell, comprising:
 a first transistor structure arranged in a first tier of the CFET cell;   a second transistor structure arranged in a second tier of the CFET cell that is above the first tier;   a first power rail arranged below the first tier and connected to the first transistor structure from below;   a second power rail formed in a first metal layer and connected to the second transistor structure from a first side;   a set of signal routing lines formed in a second metal layer that is above the second tier, wherein the set of signal routing lines is connected to the first and the second transistor structures from above; and   a signal routing structure formed in a metal zero (M0) layer and connected to the first transistor structure and/or to the second transistor structure from a second side.   
     
     
         2 . The CFET cell of  claim 1 , further comprising at least one of:
 a third transistor structure arranged in the first tier, wherein the signal routing structure is connected to the first transistor structure and the third transistor structure; or   a fourth transistor structure arranged in the second tier, wherein the signal routing structure is connected to the second transistor structure and the fourth transistor structure.   
     
     
         3 . The CFET cell of  claim 1 , wherein the signal routing structure is a three-dimensional structure configured to route signals along at least two dimensions. 
     
     
         4 . The CFET cell of  claim 1 , wherein the signal routing structure extends partly in parallel and partly perpendicular to at least one of a gate of the first transistor structure or a gate of the second transistor structure. 
     
     
         5 . The CFET cell of  claim 1 , wherein the signal routing structure comprises at least one of:
 a first part formed in a first M0 sub-layer in the first tier and connected to the first transistor structure from the second side; or   a second part formed in a second M0 sub-layer in the second tier and connected to the second transistor structure from the second side.   
     
     
         6 . The CFET cell of  claim 1 , wherein the signal routing structure is at least one of:
 connected by a M0-layer contact from the second side to a source or drain of the second transistor structure; or   connected by a M0-layer contact from the second side to a drain or source of the first transistor structure.   
     
     
         7 . The CFET cell of  claim 1 , wherein the signal routing structure is connected by a second-metal-layer contact to at least one signal routing line of the set of signal routing lines. 
     
     
         8 . The CFET cell of  claim 1 , wherein at least one of:
 a part of the second power rail is arranged in the second tier to the first side of the second transistor structure; or   a part of the second power rail is arranged in the first tier to the first side of the first transistor structure.   
     
     
         9 . The CFET cell of  claim 8 , wherein the second power rail extends vertically to a bottom side or to a top side of the CFET cell. 
     
     
         10 . The CFET cell of  claim 9 , wherein the second power rail extends to the bottom side of the CFET cell, wherein an additional signal routing line is formed in the second metal layer above the second tier and to the first side of the set of signal routing lines, and wherein the additional signal routing line is connected to the first and the second transistor structures from above. 
     
     
         11 . The CFET cell of  claim 1 , wherein the signal routing lines of the set of signal routing lines are arranged side by side, and wherein a part of the second power rail is arranged to the first side of the set of signal routing lines. 
     
     
         12 . The CFET cell of  claim 1 , wherein the second power rail has a width that is equal to or larger than two times a critical dimension of the second metal layer. 
     
     
         13 . The CFET cell of  claim 1 , wherein at least one of the signal routing lines of the set of signal routing lines is connected by a respective contact to at least one of a gate of the first transistor structure or a gate of the second transistor structure. 
     
     
         14 . The CFET cell of  claim 13 , wherein the signal routing lines of the set of signal routing lines and half of the second power rail together span a width of the CFET cell that corresponds to a track height of a 3.5 T or a 4 T CFET cell. 
     
     
         15 . A device comprising two CFET cells of  claim 1 , wherein:
 the two CFET cells are arranged side by side;   the second power rail of the two CFET cells is the same power rail; and   the second power rail of the two CFET cells is arranged between the transistor structures of first CFET cell of the two CFET cells and the transistor structures of the other one of the two CFET cells.   
     
     
         16 . The device of  claim 15 , wherein at least one of:
 a part of the second power rail of the first CFET cell is arranged in the second tier of the first CFET cell to the first side of the second transistor structure of the first CFET cell; or   a part of the second power rail of the first CFET cell is arranged in the first tier of the first CFET cell to the first side of the first transistor structure of the first CFET cell.   
     
     
         17 . The device of  claim 16 , wherein the second power rail of the first CFET cell extends vertically to a bottom side or to a top side of the first CFET cell. 
     
     
         18 . The device of  claim 17 , wherein the second power rail of the first CFET cell extends to the bottom side of the first CFET cell, wherein an additional signal routing line of the first CFET cell is formed in the second metal layer of the first CFET cell above the second tier of the first CFET cell and to the first side of the set of signal routing lines of the first CFET cell, and wherein the additional signal routing line is connected to the first and the second transistor structures of the first CFET cell from above. 
     
     
         19 . The device of  claim 15 , wherein at least one of the signal routing lines of the set of signal routing lines of the first CFET cell is connected by a respective contact to at least one of a gate of the first transistor structure of the first CFET cell or a gate of the second transistor structure of the first CFET cell. 
     
     
         20 . The device of  claim 19 , wherein the signal routing lines of the set of signal routing lines of the first CFET cell and half of the second power rail of the first CFET cell together span a width of the first CFET cell that corresponds to a track height of a 3.5 T or a 4 T CFET cell.