Interposer, method of designing interposer, and method of manufacturing interposer

Abstract

Provided is a method of manufacturing an interposer, the method including providing a design of the interposer, and manufacturing the interposer based the design of the interposer, wherein the interposer includes bump pads contacting external connection bumps and spaced apart from each other at a distance greater than a pad interval, wherein the providing the design of the interposer includes generating a library including information about library pads having different dimensions, and determining a layout of the bump pads corresponding to each of the pad regions, wherein the layout of the bump pads corresponding to each of the pad regions is determined by selecting a library pad from among the library pads having a target dimension based on the pad interval and a pitch distance of target points in each of the pad regions, and placing the selected library pad at the target points in each of the pad regions.

What is claimed is: 
     
         1 . A method of manufacturing an interposer, the method comprising:
 providing a design of the interposer; and   manufacturing the interposer based the design of the interposer,   wherein the interposer comprises bump pads contacting external connection bumps and spaced apart from each other at a distance greater than a pad interval,   wherein the providing the design of the interposer comprises:
 generating a library comprising information about library pads having different dimensions; and 
 determining a layout of the bump pads corresponding to each of the pad regions, 
 wherein the layout of the bump pads corresponding to each of the pad regions is determined by:
 selecting a library pad from among the library pads having a target dimension based on the pad interval and a pitch distance of target points in each of the pad regions; and 
 placing the selected library pad at the target points in each of the pad regions. 
 
   
     
     
         2 . The method of  claim 1 , wherein the library pads included in the library comprise:
 a first library pad having a first length in a first direction;   a second library pad having a second length that is greater than the first length in the first direction; and   a third library pad having a third length that is greater than the second length in the first direction.   
     
     
         3 . The method of  claim 2 , wherein the pad regions comprise:
 a first pad region comprising first target points spaced at a first pitch distance in the first direction;   a second pad region comprising second target points spaced at a second pitch distance that is greater than the first pitch distance in the first direction; and   a third pad region comprising third target points spaced at a third pitch distance that is greater than the second pitch distance in the first direction, and   wherein the determining of the layout of the bump pads comprises
 determining the first library pad as a bump pad at the first target points in the first pad region, 
 determining the second library pad as a bump pad at the second target points in the second pad region, and 
 determining the third library pad as a bump pad at the third target points in the third pad region. 
   
     
     
         4 . The method of  claim 3 , wherein the interposer is configured to electrically connect a semiconductor chip mounted on the interposer and the external connection bumps on the lower side of the interposer,
 wherein the first pad region comprises bump pads configured to transmit data I/O signals to the semiconductor chip, and   wherein at least one of the second pad region and the third pad region comprises bump pads configured to transmit power signals to the semiconductor chip.   
     
     
         5 . The method of  claim 2 , wherein the determining of the layout of the bump pads for each of the pad regions comprises:
 determining the first library pad as a bump pad at the target points in each of the pad regions based on the pitch distance of the target points in each of the pad regions being greater than a first reference value and less than or equal to a second reference value;   determining the second library pad as a bump pad at the target points in each of the pad regions based on the pitch distance of the target points in each of the pad regions being greater than the second reference value and less than or equal to a third reference value; and   determining the third library pad as a bump pad arranged at the target points in each of the pad regions based on the pitch distance of the target points in each of the pad regions being greater than the third reference value and less than or equal to a fourth reference value.   
     
     
         6 . The method of  claim 1 , wherein the library pads have a circular shape with a constant diameter. 
     
     
         7 . The method of  claim 1 , wherein the library pads have an elliptical shape having a major axis and a minor axis. 
     
     
         8 . The method of  claim 1 , further comprising detecting warpage on the interposer based on determining the layout of the bump pads. 
     
     
         9 . The method of  claim 1 , further comprising generating a layout drawing of the interposer comprising a layout drawing of the bump pads based on the determined layout of the bump pads. 
     
     
         10 . The method of  claim 9 , wherein the manufacturing of the interposer comprises:
 manufacturing a photo mask based on the layout drawing of the bump pads;   forming a conductive film on a side of a base substrate of the interposer; and   patterning the conductive film through a photolithography process based on the photo mask to form the bump pads.   
     
     
         11 . A method of designing an interposer, the method comprising:
 generating a library comprising information about library pads having different dimensions;   determining a layout of the bump pads corresponding to each of the pad regions, the layout of the bump pads corresponding to each of the pad regions being determined based on selecting a library pad having a target dimension from among the library pads based on a pad interval and a pitch distance of the external connection bumps overlapping each of the pad regions, and placing the selected library pad at target points in each of the pad regions; and   generating a layout drawing of the bump pads based on the determined layout of the bump pads,   wherein the interposer is configured to electrically connect a semiconductor chip mounted on the interposer and external connection bumps attached to bump pads of the interposer, and   wherein the bump pads are spaced apart from each other at a distance greater than the pad interval on a reference plane.   
     
     
         12 . The method of  claim 11 , wherein the library pads included in the library comprise:
 a first library pad having a first length in a first direction:   a second library pad having a second length that is greater than the first length in the first direction; and   a third library pad having a third length that is greater than the second length in the first direction.   
     
     
         13 . The method of  claim 12 , further comprising:
 determining the first library pad as a bump pad at the target points in each of the pad regions based on the pitch distance of the external connection bumps overlapping each of the pad regions being greater than a first reference value and less than or equal to a second reference value;   determining the second library pad as a bump pad at the target points in each of the pad regions based on the pitch distance of the external connection bumps overlapping each of the pad regions being greater than the second reference value and less than or equal to a third reference value; and   determining the third library pad as a bump pad at the target points in each of the pad regions based on the pitch distance of the external connection bumps overlapping each of the pad regions being greater than the third reference value and less than or equal to a fourth reference value.   
     
     
         14 . The method of  claim 12 , wherein the pad regions comprise a first pad region comprising bump pads configured to transmit data input/output signals to the semiconductor chip and a second pad region comprising bump pads configured to transmit power signals for the semiconductor chip,
 wherein the first pad region comprises first target points spaced at a first pitch distance in the first direction,   wherein the second pad region comprises second target points spaced at a second pitch distance that is greater than the first pitch distance in the first direction, and   wherein the determining of the layout of the bump pads comprises determining the first library pad as a bump pad at each of the first target points and determining the second library pad as a bump at each of the second target points.   
     
     
         15 . The method of  claim 11 , further comprising:
 determining whether the determined layout of the bump pads conforms to a design rule; and   detecting warpage on the interposer.   
     
     
         16 . The method of  claim 15 , wherein the library pads included in the library respectively has an elliptical shape having a major axis and a minor axis. 
     
     
         17 . An interposer comprising:
 a base substrate;   an interconnect structure on the base substrate and comprising a conductive interconnect pattern;   through electrodes penetrating the base substrate;   bump pads under the base substrate and spaced apart from each other at an interval greater than a pad interval; and   external connection bumps on the bump pads, respectively;   wherein the bump pads comprises:
 first bump pads spaced at a first pitch distance in a first pad region and respectively having a first length in a first direction; and 
 second bump pads spaced at a second pitch distance that is greater than the first pitch distance in a second pad region and respectively having a second length that is greater than the first length in the first direction. 
   
     
     
         18 . The interposer of  claim 17 , wherein the interposer is configured to electrically connect a semiconductor chip mounted on the interposer and the external connection bumps,
 wherein the first bump pads are configured to transmit data input/output signals for the semiconductor chip, and   wherein the second bump pads are configured to transmit power signals for the semiconductor chip.   
     
     
         19 . The interposer of  claim 17 , wherein the bump pads further comprise third bump pads spaced at a third pitch distance that is greater than the second pitch distance in a third pad region and respectively having a third length that is greater than the second length in the first direction. 
     
     
         20 . The interposer of  claim 19 , wherein the interposer is configured to electrically connect a semiconductor chip mounted on the interposer and the external connection bumps, and
 wherein the first bump pads, the second bump pads, and the third bump pads are dummy pads which are not electrically connected to the semiconductor chip.