Target architecture determination

Abstract

Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.

1 .- 20 . (canceled) 
     
     
         21 . An apparatus, comprising:
 a processor;   a parser, wherein the processor is coupled to the parser and is configured to cause the parser to separate a source code from other portions of source code based on a named address space defined in the source code; and   a code generator, wherein the processor is coupled to the code generator and is configured to cause the code generator to create a first portion of compiled code that includes instructions for a target architecture based on the named address space defined in the source code.   
     
     
         22 . The apparatus of  claim 21 , wherein the parser separates the source code into a number of portions based on a number of named address spaces including the named address space defined in the source code. 
     
     
         23 . The apparatus of  claim 21 , wherein the first portion of complied code includes homogeneous instructions for the target architecture. 
     
     
         24 . The apparatus of  claim 21 , wherein the target architecture is configured to execute only the first portion of compiled code. 
     
     
         25 . The apparatus of  claim 21 , wherein the processor is configured to execute only a second portion of compiled code created from the other portions of source code. 
     
     
         26 . The apparatus of  claim 21 , wherein the processor is coupled to a target identifier and the processor is configured to cause the target identifier to determine a type of target architecture based on the named address space defined in the source code. 
     
     
         27 . A method, comprising:
 creating, via a compiler, a first portion of compiled code that includes instructions for a target architecture based on a named address space defined in the source code; and   creating, via the compiler, a second portion of compiled code that includes instructions for a base processor, wherein the second portion of compiled code includes a number of instructions for the base processor.   
     
     
         28 . The method of  claim 27 , further including executing the first portion of complied code by the target architecture. 
     
     
         29 . The method of  claim 27 , further including executing the second portion of compiled code with the base processor. 
     
     
         30 . The method of  claim 27 , wherein the first portion of compiled code includes a number of instructions for the target architecture. 
     
     
         31 . The method of  claim 27 , wherein creating the first portion of compiled code includes determining a type of target architecture based on the named address space defined in the source code. 
     
     
         32 . The method of  claim 27 , wherein the named address space includes an integer to indicate the type of the target architecture. 
     
     
         33 . The method of  claim 27 , wherein the first portion of compiled code includes a number of homogeneous instructions. 
     
     
         34 . The method of  claim 27 , further comprising creating a third portion of compiled code that includes instructions for a different target architecture. 
     
     
         35 . The method of  claim 34 , wherein the third portion of compiled code is created in response to the source code having different named address spaces. 
     
     
         36 . The method of  claim 27 , wherein the target architecture is a processing in memory (PIM) architecture. 
     
     
         37 . An apparatus, comprising:
 a processor; and   a code generator, wherein the processor is coupled to the code generator and is configured to cause the code generator to create compiled code from source code based on a named address space defined in the source code.   
     
     
         38 . The apparatus of  claim 37 , wherein the compiled code includes a number of instructions for a target architecture based on a named address space defined in the source code. 
     
     
         39 . The apparatus of  claim 37 , wherein the processor is coupled to a parser and the processor is configured to cause the parser to separate the source code from other portions of source code based on the named address space defined in the source code. 
     
     
         40 . The apparatus of  claim 39 , wherein the processor is configured to cause the code generator to create compiled code from the source code for the base processor based on another named address space defined in the source code.