Display panel and display apparatus

Abstract

A display panel in one example includes pixel blocks having subpixels disposed in a display area, a bezel area disposed outside the display area, and mode control line sets individually connected to pixel blocks. Each mode control line set includes a first mode control line for supplying a first mode control signal and a second mode control line for supplying a second mode control signal. Each subpixel includes a driving transistor connected to a first power line, a first light emitting device connected to the driving transistor through a first mode control transistor controlled by the first mode control signal, a second light emitting device connected to the driving transistor through a second mode control transistor controlled by the second mode control signal, a first lens region disposed on the first light emitting device, and a second lens region disposed on the second light emitting device.

What is claimed is: 
     
         1 . A display panel comprising:
 a plurality of pixel blocks including a plurality of subpixels disposed in a display area;   a bezel area disposed outside the display area; and   a plurality of mode control line sets individually connected to the plurality of pixel blocks,   wherein each of the plurality of mode control line sets includes a first mode control line for supplying a first mode control signal and a second mode control line for supplying a second mode control signal, and   wherein each of the plurality of subpixels includes:
 a driving transistor connected to a first power line; 
 a first light emitting device connected to the driving transistor through a first mode control transistor controlled by the first mode control signal; 
 a second light emitting device connected to the driving transistor through a second mode control transistor controlled by the second mode control signal; 
 a first lens region disposed on the first light emitting device; and 
 a second lens region disposed on the second light emitting device, 
   wherein the first lens region and the second lens region differently control a viewing angle in a first direction.   
     
     
         2 . The display panel according to  claim 1 ,
 wherein each subpixel controls the viewing angle of the first direction to a wide viewing angle through the first lens region by driving the first light emitting device when the first mode control signal is activated, and   each subpixel controls the viewing angle of the first direction to a narrow viewing angle through the second lens region by driving the second light emitting device when the second mode control signal is activated.   
     
     
         3 . The display panel according to  claim 1 , wherein, in each of the plurality of pixel blocks, the first mode control line includes a first mode control line of a first type disposed in the first direction and a first mode control line of a second type disposed in a second direction different from the first direction, and
 the second mode control line includes a second mode control line of the first type disposed in the first direction and a second mode control line of the second type disposed in the second direction.   
     
     
         4 . The display panel according to  claim 3 , wherein the first mode control line of the first type and the second mode control line of the first type, which are disposed in any one pixel block among the plurality of pixel blocks, are separated from the first mode control line of the second type and the second mode control line of the second type disposed in another pixel block adjacent in the first direction. 
     
     
         5 . The display panel according to  claim 3 , wherein the first mode control line of the second type and the second mode control line of the second type, which are disposed in any one pixel block among the plurality of pixel blocks, extend in the second direction to other pixel blocks adjacent in the second direction. 
     
     
         6 . The display panel according to  claim 3 , wherein, in each of the plurality of pixel blocks, the first mode control line of the second type and the second mode control line of the second type are disposed in parallel with a second power line between each of unit pixels and extend in the second direction. 
     
     
         7 . The display panel according to  claim 3 , wherein, in each of the subpixels, a data line, an initialization voltage line, and the first power line connected to each subpixel extend in the second direction. 
     
     
         8 . The display panel according to  claim 3 ,
 wherein, in a first type pixel area included in each pixel block,   the first mode control line of the first type and the first mode control line of the second type are connected to each other through a first contact hole of an insulating layer, and   the second mode control line of the first type and the second mode control line of the second type are connected to each other through a second contact hole of an insulating layer.   
     
     
         9 . The display panel according to  claim 3 ,
 wherein, in a second type pixel area included in each pixel block,   the first mode control line of the first type intersects the first mode control line of the second type with an insulating layer interposed therebetween, and   the second mode control line of the first type intersects the second mode control line of the second type with an insulating layer interposed therebetween.   
     
     
         10 . The display panel according to  claim 3 ,
 wherein, in a third type pixel area included in each pixel block,   the first mode control line of the first type is separated from the first mode control line of the first type disposed in the adjacent pixel block, and   the second mode control line of the first type is separated from the second mode control line of the first type disposed in the adjacent pixel block.   
     
     
         11 . The display panel according to  claim 3 , wherein each of the plurality of mode control line sets includes:
 a first mode control line of a third type and a second mode control line of a third type disposed in the bezel area;   an electrostatic prevention circuit connected to each of the first mode control line of the third type and the second mode control line of the third type; and   a lighting test circuit connected to the first mode control line of the third type and the second mode control line of the third type.   
     
     
         12 . The display panel according to  claim 11 , wherein the first mode control line of the third type and the second mode control line of the third type are disposed in a data link area disposed in the bezel area or are disposed outside the data link area. 
     
     
         13 . The display panel according to  claim 11 ,
 wherein each of the plurality of mode control line sets includes:   a first mode control line of a fourth type arranged in the first direction in the bezel area, and configured to connect the first mode control line of the third type and the first mode control line of the second type; and   a second mode control line of a fourth type arranged in the first direction in the bezel area, and configured to connect the second mode control line of the third type and the second mode control line of the second type.   
     
     
         14 . The display panel according to  claim 1 , wherein each subpixel includes:
 a storage capacitor connected to a gate electrode of the driving transistor;   a first switching transistor configured to supply a data voltage of a data line to a first electrode of the storage capacitor in response to a first scan signal of a first gate line;   a second switching transistor configured to connect the driving transistor in a diode structure in response to a second scan signal of a second gate line;   a third switching transistor configured to supply an initialization voltage of an initialization voltage line to the first electrode of the storage capacitor in response to an emission control signal of a third gate line;   a fourth switching transistor configured to connect the driving transistor and the first and second mode control transistors in response to the emission control signal of the third gate line;   a fifth switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the second light emitting device in response to the second scan signal of the second gate line; and   a seventh switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the first light emitting device in response to the second scan signal of the second gate line.   
     
     
         15 . The display panel according to  claim 1 ,
 wherein the first light emitting device includes a first light emitting area, and   the first lens region includes a first lens which overlaps the first light emitting area and has a bottom surface which is wider than a bottom surface of the first light emitting area.   
     
     
         16 . The display panel according to  claim 1 ,
 wherein the second light emitting device includes a plurality of second light emitting areas,   the second lens region includes a plurality of second lenses overlapped with the plurality of second light emitting areas, and   each of the plurality of second lenses includes a bottom surface which is wider than a bottom surface of each of at least one of the plurality of second light emitting areas.   
     
     
         17 . The display panel according to  claim 1 ,
 wherein the plurality of subpixels include a first color subpixel, a second color subpixel, and a third color subpixel,   a size of the first lens in the first lens region in each of the first, second, and third color subpixels is different from each other, and   the number of second lenses in the second lens region in each of the first, second, and third color subpixels is different from each other.   
     
     
         18 . The display panel according to  claim 1 , wherein the first lens region and the second lens region control the viewing angle identically in a second direction vertical to the first direction. 
     
     
         19 . The display panel according to  claim 1 , wherein a first lens in the first lens region is a half-cylindrical lens elongated in the first direction, and a second lens in the second lens region is a half-spherical lens. 
     
     
         20 . The display panel according to  claim 17 ,
 wherein the first color subpixel, the second color subpixel, and the third color subpixel are a red subpixel, a green subpixel and a blue subpixel respectively,   wherein a number of the second lenses disposed in the second lens region of the blue subpixel is greater than a number of the second lenses disposed in the second lens region of the red subpixel, and is greater than a number of the second lenses disposed in the second lens region of the green subpixel, and   wherein a number of the second lenses disposed in the second lens region of the green subpixel area is greater than a number of the second lenses disposed in the second lens region of the red subpixel.   
     
     
         21 . The display panel according to  claim 17 ,
 wherein the first color subpixel, the second color subpixel, and the third color subpixel are a red subpixel, a green subpixel and a blue subpixel respectively,   wherein a size of the first lenses disposed in the first lens region of the blue subpixel is greater than a size of the first lenses disposed in the first lens region of the red subpixel, and is greater than a size of the first lenses disposed in the first lens region of the green subpixel, and   wherein a size of the first lenses disposed in the first lens region of the green subpixel area is greater than a size of the first lenses disposed in the first lens region of the red subpixel.   
     
     
         22 . The display panel according to  claim 12 ,
 wherein a chip on film is disposed in the bezel region, and   wherein the data link area is located between the chip on film and the display area.   
     
     
         23 . The display panel according to  claim 14 ,
 wherein the third gate line and the first gate line are arranged in the first direction at a lower end portion with respect to the driving transistor and the storage capacitor, and   wherein the second gate line, the second mode control line, the third gate line, the first mode control line, and the second gate line are arranged in the first direction at an upper end portion with respect to the driving transistor and the storage capacitor.   
     
     
         24 . The display panel according to  claim 11 , wherein in an area corresponding to the electrostatic prevention circuit and the lighting test circuit in the bezel area, a plurality of data input lines, the first and second mode control lines of the third type, and a plurality of power input lines are disposed in parallel in the first direction and extend in the second direction. 
     
     
         25 . The display panel according to  claim 24 , wherein the electrostatic prevention circuit is operated when static electricity is introduced through any one of the plurality of data input lines and the first and second mode control lines of the third type, and is configured to discharge static electricity through an electrostatic discharge line. 
     
     
         26 . A display apparatus comprising:
 the display panel of  claim 1 ; and   a data driver disposed in the bezel area and configured to drive data lines disposed in the display area,   wherein the data driver individually supplies the first mode control signal and the second mode control signal to each of the plurality of mode control line sets.