Semiconductor package

Abstract

A semiconductor package includes a package-bottom redistribution structure at a lower side of a package and including a conductive line, an upper semiconductor chip at an upper side of the package, an upper back end of line (BEOL) layer, at a lower side of the upper semiconductor chip, and including a conductive line, a lower semiconductor chip below the upper semiconductor chip, where a horizontal width of the lower semiconductor chip is less than a horizontal width of the upper semiconductor chip, and where the upper semiconductor chip overlaps at least a portion of the lower semiconductor chip, a lower BEOL layer at a lower side of the lower semiconductor chip and including a conductive line, a passivation layer on an upper surface of the lower semiconductor chip, and a through silicon via (TSV) structure penetrating the passivation layer and the lower semiconductor chip.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a package-bottom redistribution structure at a lower side of a package and comprising a conductive line;   an upper semiconductor chip at an upper side of the package;   an upper back end of line (BEOL) layer, at a lower side of the upper semiconductor chip, comprising a conductive line;   a lower semiconductor chip below the upper semiconductor chip, wherein a horizontal width of the lower semiconductor chip is less than a horizontal width of the upper semiconductor chip, and wherein at least a portion of the upper semiconductor chip overlaps the lower semiconductor chip;   a lower BEOL layer at a lower side of the lower semiconductor chip and comprising a conductive line;   a passivation layer on an upper surface of the lower semiconductor chip;   a through silicon via (TSV) structure penetrating the passivation layer and the lower semiconductor chip, the TSV structure being connected to the conductive line of the lower BEOL layer;   a first redistribution line connected to the TSV structure, wherein at least a portion of the first redistribution line is impregnated in the passivation layer;   a second redistribution line above the first redistribution line and connected to the first redistribution line through an intermediate via;   a first intermediate insulating layer on the passivation layer, separating the first redistribution line from the second redistribution line and at least partially surrounding the intermediate via;   a second intermediate insulating layer on the first intermediate insulating layer and at least partially surrounding the second redistribution line;   an inter-chip connection structure between the second intermediate insulating layer and the upper BEOL layer, the inter-chip connection structure connecting the conductive line of the upper BEOL layer and the second redistribution line;   a first post connecting the conductive line of the lower BEOL layer and the conductive line of the package-bottom redistribution structure;   a second post connecting the conductive line of the upper BEOL layer and the conductive line of the package-bottom redistribution structure;   a first molding layer between the lower BEOL layer and the package-bottom redistribution structure, the first molding layer at least partially surrounding the first post; and   a second molding layer between the upper BEOL layer and the package-bottom redistribution structure, the second molding layer at least partially surrounding the second post.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the TSV structure comprises an exposed interface on an upper end thereof, and
 wherein at least a portion of an upper surface of the first redistribution line is not above the exposed interface of the upper end of the TSV structure.   
     
     
         3 . The semiconductor package of  claim 2 , wherein the intermediate via is on the at least a portion of the upper surface of the first redistribution line that is not vertically above the exposed interface of the upper end of the TSV structure. 
     
     
         4 . The semiconductor package of  claim 2 , wherein a lower surface of the first redistribution line is below the exposed interface of the upper end of the TSV structure. 
     
     
         5 . The semiconductor package of  claim 2 , wherein at least another portion of the upper surface of the first redistribution line is vertically above the exposed interface of the upper end of the TSV structure. 
     
     
         6 . The semiconductor package of  claim 1 , wherein a portion of the TSV structure extends into the passivation layer, and
 wherein the portion of the TSV structure that extends into the passivation layer is at least partially surrounded while contacting the first redistribution line.   
     
     
         7 . The semiconductor package of  claim 1 , further comprising a dummy redistribution line comprising a material that is substantially the same as a material the second redistribution line, and
 wherein the dummy redistribution line is horizontally at a level as that is substantially the same as a level the second redistribution line.   
     
     
         8 . A semiconductor package comprising:
 a lower semiconductor chip at a lower side of a package;   a lower back end of line (BEOL) layer, at a lower side of the lower semiconductor chip, comprising a conductive line;   an upper semiconductor chip above the lower semiconductor chip, wherein a horizontal width of the upper semiconductor chip is less than a horizontal width of the lower semiconductor chip, and wherein the upper semiconductor chip overlaps at least a portion of the lower semiconductor chip;   an upper BEOL layer at a lower side of the upper semiconductor chip and comprising a conductive line;   a passivation layer on an upper surface of the lower semiconductor chip;   a through silicon via (TSV) structure penetrating the passivation layer and the lower semiconductor chip, the TSV structure being connected to the conductive line of the lower BEOL layer;   a first redistribution line connected to the TSV structure, wherein at least a portion of the first redistribution line is impregnated in the passivation layer;   a second redistribution line above the first redistribution line and connected to the first redistribution line through an intermediate via;   a first intermediate insulating layer on the passivation layer, separating the first redistribution line from the second redistribution line and at least partially surrounding the intermediate via;   a second intermediate insulating layer on the first intermediate insulating layer and at least partially surrounding the second redistribution line;   an inter-chip connection structure between the second intermediate insulating layer and the upper BEOL layer, the inter-chip connection structure connecting the conductive line of the upper BEOL layer to the second redistribution line; and   a molding layer above the lower semiconductor chip and at least partially surrounding the upper semiconductor chip.   
     
     
         9 . The semiconductor package of  claim 8 , wherein the TSV structure comprises an exposed interface on an upper end thereof, and
 wherein at least a portion of an upper surface of the first redistribution line is not above the exposed interface of the upper end of the TSV structure.   
     
     
         10 . The semiconductor package of  claim 9 , wherein the intermediate is on the at least a portion of the upper surface of the first redistribution line that is not positioned above the exposed interface of the upper end of the TSV structure. 
     
     
         11 . The semiconductor package of  claim 9 , wherein a lower surface of the first redistribution line is below the exposed interface of the upper end of the TSV structure. 
     
     
         12 . The semiconductor package of  claim 9 , wherein at least another portion of the upper surface of the first redistribution line is above the exposed interface of the upper end of the TSV structure. 
     
     
         13 . The semiconductor package of  claim 8 , wherein a portion of the TSV structure extends into the passivation layer, and
 wherein the portion of the TSV structure that extends into the passivation layer is at least partially surrounded while contacting the first redistribution line.   
     
     
         14 . The semiconductor package of  claim 8 , further comprising a dummy redistribution line comprising a material that is substantially the same as a material of the second redistribution line, and
 wherein the dummy redistribution line is horizontally at a level that is substantially the same as a level of the second redistribution line.   
     
     
         15 . A semiconductor package comprising:
 a semiconductor chip;   a back end of line (BEOL) layer, at a lower side of the semiconductor chip, comprising a conductive line;   a passivation layer on an upper surface of the semiconductor chip;   a through silicon via (TSV) structure penetrating the passivation layer and the semiconductor chip, the TSV structure being electrically connected to the conductive line of the BEOL layer;   a first redistribution line connected to the TSV structure, wherein at least a portion of the first redistribution line is impregnated in the passivation layer;   a second redistribution line above the first redistribution line and connected to the first redistribution line through an intermediate via;   a first intermediate insulating layer on the passivation layer, separating the first redistribution line from the second redistribution line and at least partially surrounding the intermediate via; and   a second intermediate insulating layer on the first intermediate insulating layer and at least partially surrounding the second redistribution line.   
     
     
         16 . The semiconductor package of  claim 15 , wherein the TSV structure comprises an exposed interface on an upper end thereof, and
 wherein at least a portion of an upper surface of the first redistribution line is not above the exposed interface of the upper end of the TSV structure.   
     
     
         17 . The semiconductor package of  claim 16 , wherein the intermediate is on the at least a portion of the upper surface of the first redistribution line that is not above the exposed interface of the upper end of the TSV structure. 
     
     
         18 . The semiconductor package of  claim 16 , wherein a lower surface of the first redistribution line is below the exposed interface of the upper end of the TSV structure. 
     
     
         19 . The semiconductor package of  claim 16 , wherein at least another portion of the upper surface of the first redistribution line is above the exposed interface of the upper end of the TSV structure. 
     
     
         20 . The semiconductor package of  claim 15 , wherein a portion of the TSV structure extends into the passivation layer, and
 wherein the portion of the TSV structure that extends into the passivation layer is at least partially surrounded while contacting the first redistribution line.