Three-dimensional memory device and method of making thereof including expanded support openings and double spacer word line contact formation

Abstract

A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

What is claimed is: 
     
         1 . A memory device, comprising:
 at least one alternating stack of insulating layers and electrically conductive layers;   memory stack structures vertically extending through the at least one alternating stack, wherein each of the memory stack structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel;   an electrically conductive layer contact via structure vertically extending through an upper portion of the at least one alternating stack and contacting a top surface of one of the electrically conductive layers;   a plurality of support pillar structures having at least a dielectric outer sidewall vertically extending through each layer within the at least one alternating stack and contacting a respective first sidewall segment of the layer contact via structure; and   a plurality of dielectric spacers vertically extending through the upper portion of the at least one alternating stack and contacting a respective second sidewall segment of the layer contact via structure.   
     
     
         2 . The memory device of  claim 1 , wherein:
 the plurality of support pillar structures comprises a plurality of dielectric support pillar structures; and   the plurality of dielectric support pillar structures and the plurality of dielectric spacers are azimuthally interlaced around a vertical axis passing through a center of the layer contact via structure.   
     
     
         3 . The memory device of  claim 2 , wherein:
 the plurality of dielectric support pillar structures comprises P dielectric support pillar structures; and   P is an integer greater than 1.   
     
     
         4 . The memory device of  claim 3 , wherein each of the plurality of dielectric spacers is located within a respective azimuthal angle range around the vertical axis that has a magnitude less than 2π/P radian. 
     
     
         5 . The memory device of  claim 3 , wherein:
 the at least one alternating stack comprises M alternating stacks, in which M is an integer greater than 1;   the plurality of dielectric spacers comprises a total of M×P dielectric spacers; and   the M×P dielectric spacers comprises M sets of P dielectric spacers that are azimuthally spaced apart around the vertical axis, wherein each set of respective P dielectric spacers overlies or underlies any other set of respective P dielectric spacers.   
     
     
         6 . The memory device of  claim 2 , wherein:
 each of the plurality of dielectric support pillar structures has a respective center and a respective vertical axis passing through the respective center; and   each of the vertical axes of the plurality of dielectric support pillar structures is laterally spaced from the vertical axis passing through the center of the layer contact via structure by a greater lateral distance than any point within the plurality of dielectric spacers is from the vertical axis passing through the center of the layer contact via structure.   
     
     
         7 . The memory device of  claim 1 , wherein at least one of the plurality of dielectric support pillar structures comprises a lower portion which is located under a bottom surface of the layer contact via structure. 
     
     
         8 . The memory device of  claim 1 , wherein each surface segment of the layer contact via structure located above a horizontal plane including a top surface of the one of the electrically conductive layers and below a horizontal surface including a topmost surface of the at least one alternating stack is in direct contact with one of plurality of support pillar structures or with one of the plurality of dielectric spacers. 
     
     
         9 . The memory device of  claim 1 , wherein each interface between the layer contact via structure and the plurality of support pillar structures has a horizontal cross-sectional profile in which a convex surface segment of the layer contact via structure is in direct contact with a concave surface segment of a respective one of the support pillar structures. 
     
     
         10 . The memory device of  claim 1 , wherein:
 each of the plurality of support pillar structures is in direct contact with a respective pair of dielectric spacers of the plurality of dielectric spacers; and   each of the plurality of dielectric spacers is in direct contact with a respective pair of the support pillar structures.   
     
     
         11 . The memory device of  claim 1 , wherein:
 each of the plurality of support pillar structures is in direct contact with each insulating layer within the at least one alternating stack; and   each insulating layer within the at least one alternating stack that overlies the one of the electrically conductive layers is in direct contact with at least two dielectric spacers of the plurality of dielectric spacers.   
     
     
         12 . The memory device of  claim 1 , further comprising a contact-level dielectric layer that overlies the at least one alternating stack, wherein:
 top surfaces of the plurality of support pillar structures located within a horizontal plane including a top surface of the contact-level dielectric layer; and   topmost surfaces of the plurality of dielectric spacers are located within a horizontal plane including top surfaces of the at least one alternating stack.   
     
     
         13 . The memory device of  claim 1 , wherein each interface between the layer contact via structure and a respective one of the plurality of support pillar structures vertically extends from the one of the electrically conductive layers to a horizontal plane including a topmost surface of the at least one alternating stack. 
     
     
         14 . The memory device of  claim 1 , wherein each of the plurality of dielectric spacers comprises at least one laterally-extending fin portion which is located at a level of a respective one of the electrically conductive layers, has a respective horizontally-extending top surface contacting a respective overlying insulating layer within the at least one alternating stack, and has a respective horizontally-extending bottom surface segment contacting a respective underlying insulating layer within the at least one alternating stack. 
     
     
         15 . The memory device of  claim 1 , further comprising:
 additional memory stack structures vertically extending through the at least one alternating stack, wherein the memory stack structure and the additional memory stack structures comprise a three-dimensional array of memory elements; and   the electrically conductive layers comprise word lines for the three-dimensional array of memory elements.   
     
     
         16 . A method of forming a semiconductor structure, comprising:
 forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate;   forming first sacrificial pillar structures through the first alternating stack;   forming a first via cavity through a subset of layers within the first alternating stack;   forming a first sacrificial via fill structure in a volume of the first via cavity;   forming pillar cavities by removing at least the first sacrificial pillar structures;   laterally expanding at least some of the pillar cavities by performing at least one isotropic etch process;   forming dielectric pillar structures in the laterally expanded pillar cavities;   replacing the first sacrificial material layers with first electrically conductive layers; and   replacing the via-shaped material portion with an electrically conductive layer contact via structure that directly contacts a top surface of one of the first electrically conductive layers.   
     
     
         17 . The method of  claim 16 , further comprising:
 forming memory openings through the at least one alternating stack; and   forming memory stack structures in the memory openings, wherein each of the memory stack structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel.   
     
     
         18 . The method of  claim 16 , wherein:
 at least one of the plurality of dielectric support pillar structures comprises a lower portion which is located under a bottom surface of the layer contact via structure;   a via-shaped material portion occupying a volume of the first sacrificial via fill structure is physically exposed to a subset of laterally expanded pillar cavities after the step of laterally expanding the pillar cavities; and   each exposed surface of the via-shaped material portion that is exposed to a respective one of the pillar cavities continuously extends from a top surface of the via-shaped material portion to a bottom surface of the via-shaped material portion.   
     
     
         19 . The method of  claim 16 , further comprising forming a tubular dielectric spacer in a peripheral portion of the first via cavity, wherein:
 the via-shaped material portion is formed inside the tubular dielectric spacer;   the at least one isotropic etch process etches portions of the tubular dielectric spacer; and   the tubular dielectric spacer is divided into a plurality of dielectric spacers that are azimuthally spaced apart around the via-shaped material portion.   
     
     
         20 . The method of  claim 16 , further comprising:
 forming a second alternating stack of second insulating layers and first sacrificial material layers over the first alternating stack prior to forming the pillar cavities;   forming second sacrificial pillar structures through the second alternating stack;   forming a second via cavity through the alternating stack on a top surface of the first sacrificial via fill structure; and   forming a second sacrificial via fill structure in a volume of the second via cavity, wherein the pillar cavities are formed by removing the second sacrificial pillar structure in addition to the first sacrificial pillar structures, and wherein each of the pillar cavities comprises a respective void formed by removal of a respective one of the second sacrificial pillar structures, wherein the via-shaped material portion is formed by replacement, or incorporation, the second sacrificial via fill structure.