Processor and method of controlling processor

Abstract

A processor includes an instruction execution circuit configured to execute an instruction; an instruction supply circuit configured to output the instruction to be executed by the instruction execution circuit; and an instruction selection circuit configured to output the instruction received from the instruction supply circuit to the instruction execution circuit, and output another instruction to the instruction execution circuit in response to detecting that instruction reception from the instruction supply circuit is stopped.

What is claimed is: 
     
         1 . A processor comprising:
 an instruction execution circuit configured to execute an instruction;   an instruction supply circuit configured to output the instruction to be executed by the instruction execution circuit; and   an instruction selection circuit configured to output the instruction received from the instruction supply circuit to the instruction execution circuit, and output another instruction to the instruction execution circuit in response to detecting that instruction reception from the instruction supply circuit is stopped.   
     
     
         2 . The processor as claimed in  claim 1 , wherein the another instruction is at least one of an instruction that is the same as a first instruction received from the instruction supply circuit before the instruction reception from the instruction supply circuit is stopped, an instruction based on the first instruction, or an instruction determined based on power consumption of the first instruction. 
     
     
         3 . The processor as claimed in  claim 2 , wherein the first instruction is an instruction received from the instruction supply circuit immediately before the instruction reception from the instruction supply circuit is stopped. 
     
     
         4 . The processor as claimed in  claim 1 , wherein the another instruction is an instruction determined based on power consumption. 
     
     
         5 . The processor as claimed in  claim 1 , wherein the instruction selection circuit outputs the another instruction so that the instruction execution circuit continuously executes a same instruction two or more times, in response to detecting that the instruction reception from the instruction supply circuit is stopped. 
     
     
         6 . The processor as claimed in  claim 1 , further comprising a memory to which an execution result of the instruction by the instruction execution circuit is written,
 wherein an execution result of the another instruction is not written to the memory.   
     
     
         7 . The processor as claimed in  claim 1 , further comprising an instruction hold circuit configured to hold the instruction output by the instruction supply circuit,
 wherein the another instruction is an instruction held in the instruction hold circuit.   
     
     
         8 . The processor as claimed in  claim 7 , wherein the another instruction is an instruction held in the instruction hold circuit immediately before the instruction reception from the instruction supply circuit is stopped. 
     
     
         9 . The processor as claimed in  claim 7 , further comprising a memory to which an execution result of the instruction by the instruction execution circuit is written,
 wherein the holding of the instruction output by the instruction supply circuit includes holding the instruction by changing the instruction output by the instruction supply circuit to an instruction for preventing the execution result from being written to the memory, and   wherein the another instruction is the changed and held instruction.   
     
     
         10 . The processor as claimed in  claim 7 , wherein the instruction supply circuit outputs, to the instruction selection circuit, a selection signal for causing the instruction held in the instruction hold circuit to be output, in response to detecting that there is no instruction to be output to the instruction execution circuit. 
     
     
         11 . The processor as claimed in  claim 7 , wherein the instruction supply circuit outputs, to the instruction selection circuit, a selection signal for causing the instruction held in the instruction hold circuit to be output, in response to receiving a wait instruction generated when the instruction execution circuit cannot execute an instruction. 
     
     
         12 . The processor as claimed in  claim 7 , further comprising a selection control circuit configured to output, to the instruction selection circuit, a selection signal for causing the instruction held in the instruction hold circuit to be output, in response to detecting that the instruction supply circuit outputs no instruction or the instruction execution circuit cannot execute an instruction. 
     
     
         13 . The processor as claimed in  claim 1 , wherein the instruction selection circuit outputs the another instruction to the instruction execution circuit a plurality of times until the instruction reception from the instruction supply circuit is restarted. 
     
     
         14 . The processor as claimed in  claim 1 , wherein the instruction execution circuit includes a plurality of arithmetic units and operates as a single instruction multiple data (SIMD) processor. 
     
     
         15 . A method of controlling a processor including an instruction execution circuit configured to execute an instruction and an instruction supply circuit configured to output the instruction to be executed by the instruction execution circuit, the method comprising:
 outputting, by an instruction selection circuit included in the processor, the instruction received from the instruction supply circuit to the instruction execution circuit, and outputting another instruction to the instruction execution circuit, in response to detecting that instruction reception from the instruction supply circuit is stopped.   
     
     
         16 . The method as claimed in  claim 15 , wherein the another instruction is at least one of an instruction that is the same as a first instruction received from the instruction supply circuit before the instruction reception from the instruction supply circuit is stopped, an instruction based on the first instruction, or an instruction determined based on power consumption of the first instruction. 
     
     
         17 . The method as claimed in  claim 15 , wherein the another instruction is an instruction determined based on power consumption. 
     
     
         18 . The method as claimed in  claim 15 , wherein the outputting of the another instruction includes outputting the another instruction so that the instruction execution circuit continuously executes a same instruction two or more times, in response to detecting that the instruction reception from the instruction supply circuit is stopped. 
     
     
         19 . The method as claimed in  claim 15 , further comprising wiring, by the instruction execution circuit, an execution result of the instruction to a memory, wherein an execution result of the another instruction is not written to the memory. 
     
     
         20 . The method as claimed in  claim 15 , further comprising holding, by an instruction hold circuit included in the processor, the instruction output by the instruction supply circuit,
 wherein the another instruction is an instruction held in the instruction hold circuit.   
     
     
         21 . The method as claimed in  claim 15 , wherein the outputting of the another instruction includes outputting the another instruction to the instruction execution circuit a plurality of times until the instruction reception from the instruction supply circuit is restarted.