Memory system

Abstract

A memory system for low power consumption and high speed read operation in the memory system includes a source line, a string select line having i layers, a first word line having i layers, a second word line having i layers, a select gate line having 1 layer which is divided into 2n, a plurality of memory pillars and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string includes a first transistor, i first memory cells and j second memory cells. The first transistor, the i first memory cells, and the j second memory cells are electrically connected in series. The second string includes a second transistor, i third memory cells, and j fourth memory cells. The second transistor, the i third memory cells, and the j fourth memory cells are electrically connected in series.

What is clamed is: 
     
         1 . A memory system comprising:
 a source line expanding to a first direction and a second direction intersecting with the first direction;   a string select line having j layers (“j” is one or more integer number) and provided in a third direction intersecting the first direction and the second direction with respect to the source line;   a first word line having i layers (“i” is two or more integer number) stacked in the third direction and provided in the third direction with respect to the string select line;   a second word line having i layers, provided in the third direction with respect to the string select line and stacked in the third direction, a position of the second word line having i layers in the third direction being the same as the first word line having i layers;   a select gate line having 1 layer provided in the third direction with respect to the first word line and the second word line, and divided into 2n (“n” is one or more integer number) in a plan expanding to the first direction and the second direction;   a plurality of memory pillars having semiconductor layers, provided between the first word line and the second word line, provided between the select gate lines facing each other among the 2n select gate lines, and extended in the third direction; and   a control circuit,   wherein   the plurality of memory pillars is electrically connected to the source line,   each of the plurality of memory pillars has a first string provided in a first side of the memory pillar and a second string provided in a second side of the memory pillar,   the first string has a first transistor, i first memory cells and j second memory cells,   the i first memory cells are provided between the first transistor and the second memory cell closest to the first transistor among the j second memory cells,   the first transistor, the i memory cells, and the j second memory cells are electrically connected in series,   the first transistor is connected to one of the select gate line among the 2n select gate lines,   the i first memory cells are electrically connected in series, provided along the third direction, and respectively connected to the first word line having i layers,   the second string has a second transistor, i third memory cells, and j fourth memory cells,   the i third memory cells are provided between the second transistor and the fourth memory cell closest to the second transistor among the j fourth memory cells,   the second transistor, the i third memory cells and the j fourth memory cells are electrically connected in series,   the second transistor is connected to one of the select gate line among the 2n select gate lines,   the i third memory cells are electrically connected in series, provided along the third direction, and respectively connected to the second word line having i layers,   a position of the #1 first word line among the first word line having i layers is the closest to a position of the source line, and a position of the #i first word line is the farthest from the position of the source line,   a position of the #1 second word line among the second word line having i layers is the closest to the position of the source line and a position of the #i second word line is the farthest from the position of the source line,   the i first memory cells and the i third memory cells share the semiconductor layer, and   j is no larger than n in the second memory cell and the fourth memory cell.   
     
     
         2 . The memory system according to  claim 1 , wherein
 the select gate line includes a first select gate line, a second select gate line, a third select gate line and a fourth select gate line,   the first select gate line faces the second select gate line,   the third select gate line faces the fourth select gate line,   the plurality of memory pillars includes a first memory pillar and a second memory pillar,   the first memory pillar includes a target memory cell in a read operation and is sandwiched by the first select gate line and the second select gate line,   the second memory pillar is sandwiched by the third select gate line and the fourth select gate line, and   the control circuit is configured to
 control all of the j second memory cells and the j fourth memory cells included in the first memory pillar to an on-state, and 
 control one of the j second memory cells included in the second memory pillar and one of the j fourth memory cells included in the second memory pillar to an off-state. 
   
     
     
         3 . The memory system according to  claim 1 , wherein
 the select gate line includes a first select gate line, a second select gate line, a third select gate line, and a fourth select gate line,   the first select gate line faces the second select gate line,   the second select gate line faces the third select gate line,   the third select gate line faces the fourth select gate line,   the plurality of memory pillars includes a first memory pillar, a second memory pillar, and a third memory pillar,   the first memory pillar includes a target memory cell in a read operation and is sandwiched by the first select gate line and the second select gate line,   the third memory pillar is sandwiched by the second select gate line and the third select gate line,   the second memory pillar is sandwiched by the third select gate line and the fourth select gate line, and   the control circuit is configured to
 control all of the j second memory cells and the j fourth memory cells included in each of the first memory pillar and the third memory pillar to an on-state, and 
 control one of the j second memory cells included in the second memory pillar and one of the j fourth memory cells included in the second memory pillar to an off-state. 
   
     
     
         4 . The memory system according to  claim 3 , wherein
 the control circuit is configured to control the first transistor, the i first memory cells, the j second memory cells, the second transistor, the i third memory cells and the j fourth memory cells included in the third memory pillar to the on-state.   
     
     
         5 . The memory system according to  claim 1 , wherein
 the select gate line includes a first select gate line and a second select gate line,   the first select gate line faces the second select gate line,   the plurality of memory pillars includes a first memory pillar, a second memory pillar, a third memory pillar, and a fourth memory pillar,   the first memory pillar is sandwiched by the first select gate line and the second select gate line,   the second memory pillar is not adjacent to any one of the first select gate line and the second select gate line,   the third memory pillar is not adjacent to the first select gate line and is adjacent to the second select gate line,   the fourth memory pillar is not adjacent to the second select gate line and is adjacent to the first select gate line, and   the control circuit is configured to control the second memory cell and the fourth memory cell belonging to a memory pillar group with the first memory pillar, the third memory pillar, and the fourth memory pillar as the memory pillar group.   
     
     
         6 . The memory system according to  claim 5  wherein
 one of the second memory cells among the j second memory cells is in an erased state and the other of the second memory cells are in a written state, and 
 the control circuit is configured to commonly control all of the second memory cells belonging the memory pillar group. 
 
     
     
         7 . The memory system according to  claim 5 , wherein
 a plurality of the second memory cells among the j second memory cells is an erased state and the other of the second memory cells are written state, and   the control circuit is configured to commonly control all of the second memory cells belonging the memory pillar group.   
     
     
         8 . The memory system according to  claim 1 , wherein
 the select gate line includes a first select gate line and a second select gate line,   the first select gate line faces the second select gate line,   the plurality of memory pillars includes a first memory pillar, a second memory pillar, a third memory pillar, and a fourth memory pillar,   the first memory pillar is sandwiched by the first select gate line and the second select gate line,   the second memory pillar is not adjacent to any one of the first select gate line and the second select gate line,   the third memory pillar is not adjacent to the first select gate line and is adjacent to the second select gate line,   the fourth memory pillar is not adjacent to the second select gate line and is adjacent to the first select gate line,   the j second memory cells and the j fourth memory cells share the semiconductor layer, and   the control circuit is configured to select a target memory pillar for read operation from the first memory pillar, the second memory pillar, the third memory pillar, and the fourth memory pillar by supplying different voltage to the string select line connected to the memory cell and the string select line connected to the fourth memory cell.