Programmable optimized band switching lna

Abstract

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

1 . A front-end circuit comprising:
 an input port configured to receive an input signal, wherein the input signal has a frequency within one of at least two frequency ranges;   an output port configured to provide an output signal, wherein the output signal is an amplified version of the received input signal;   a low noise amplifier (LNA) comprising an LNA input coupled to the input port and an LNA output;   an output impedance matching network coupled between the LNA output and the output port; and   a first switched impedance circuit (SIC) having a selectable impedance value and configured to have an impedance value based at least in part on the frequency of the input signal, wherein the selectable impedance value is based on a plurality of selectable impedances, wherein the first SIC is coupled in parallel with the output impedance matching network and coupled to the LNA output and to the output port.   
     
     
         2 . The front-end circuit of  claim 1 , wherein the first SIC comprises:
 a first terminal coupled to the LNA output;   a second terminal coupled to the output port; and   a plurality of legs in parallel with each other and coupled between the first terminal and the second terminal, wherein each of the plurality of legs comprises a respective impedance element and a respective switch in series with the respective impedance element, and wherein each leg of the first SIC has a respective first impedance value when the respective switch is closed and a respective second impedance value when the respective switch is open.   
     
     
         3 . The front-end circuit of  claim 2 , wherein the switch of each of the plurality of legs is configured to be open or closed based at least in part on the frequency of the input signal to control the impedance value of the first SIC, and wherein the plurality of legs comprises:
 a first leg comprising a first capacitor as its impedance element and a first switch in series with the first capacitor;   a second leg comprising a second capacitor as its impedance element and a second switch in series with the second capacitor; and   a third leg comprising a third capacitor as its impedance element and a third switch in series with the third capacitor.   
     
     
         4 . The front-end circuit of  claim 2 , wherein at least three legs of the plurality of legs comprises a respective capacitor as its respective impedance element connected to the first terminal. 
     
     
         5 . The front-end circuit of  claim 1 , further comprising a second SIC having a selectable impedance value and coupled to the LNA output and ground, wherein the second SIC comprises:
 a first terminal coupled to the LNA output;   a second terminal coupled to ground; and   a plurality of legs in parallel with each other and coupled between the first terminal and the second terminal, wherein each of the plurality of legs comprises a respective impedance element and a respective switch in series with the respective impedance element, and wherein each leg of the second SIC has a respective first impedance value when the switch is closed and a respective second impedance value when the switch is open.   
     
     
         6 . The front-end circuit of  claim 5 , wherein the switch of each of the plurality of legs is configured to be open or closed based at least in part on the frequency of the input signal to control the impedance value of the second SIC, and wherein the plurality of legs comprises:
 a first leg comprising a first impedance element and a first switch in series with the first impedance element;   a second leg comprising a second impedance element and a second switch in series with the second impedance element; and   a third leg comprising a third impedance element and a third switch in series with the third impedance element.   
     
     
         7 . The front-end circuit of  claim 6 , wherein the plurality of legs further comprises a fourth leg comprising a fourth impedance element and a fourth switch in series with the fourth impedance element. 
     
     
         8 . The front-end circuit of  claim 7 , further comprising a fifth impedance element coupled to the plurality of legs and to the LNA output, wherein:
 each of the first, second, third, and fourth impedance elements comprises a respective capacitor; or   each of the first, second, third, and fourth impedance elements comprises a respective resistor.   
     
     
         9 . The front-end circuit of  claim 7 , wherein:
 the plurality of legs further comprises:
 a fifth leg comprising a fifth impedance element and a fifth switch in series with the fifth impedance element; 
 a sixth leg comprising a sixth impedance element and a sixth switch in series with the sixth impedance element; 
 a seventh leg comprising a seventh impedance element and a seventh switch in series with the seventh impedance element; and 
 an eighth leg comprising an eighth impedance element and an eighth switch in series with the eighth impedance element; 
   the front-end circuit further comprises a ninth impedance element coupled to the plurality of legs and to the LNA output;   each of the first, second, third, and fourth impedance elements comprises a respective capacitor; and   each of the fifth, sixth, seventh, and eighth impedance elements comprises a respective resistor.   
     
     
         10 . The front-end circuit of  claim 1 , further comprising a bias control module configured to:
 generate a bias voltage; and   provide the bias voltage to a transistor of the LNA, wherein a gain associated with the LNA is based at least in part on the bias voltage.   
     
     
         11 . The front-end circuit of  claim 10 , wherein the LNA is configured to provide an LNA output signal to the LNA output based on the input signal received at the LNA input, wherein the input signal received at the LNA input is based on the input signal received at the input port, wherein the bias control module is further configured to receive one or more input signals from a central control processor, and wherein the bias control module is configured to generate the bias voltage based on the one or more input signals. 
     
     
         12 . The front-end circuit of  claim 10 , wherein the bias control module is configured to generate the bias voltage based at least in part on the frequency of the input signal. 
     
     
         13 . The front-end circuit of  claim 1 , wherein:
 the LNA comprises:
 a first transistor coupled to the LNA input; and 
 a second transistor coupled to the first transistor and to the LNA output; and 
   the front-end circuit further comprises a bias control module configured to:
 generate a bias voltage; and 
 provide the bias voltage to the second transistor, wherein a gain associated with the LNA is based at least in part on the bias voltage. 
   
     
     
         14 . The front-end circuit of  claim 13 , further comprising:
 a third SIC having a selectable impedance value and coupled to a gate of the first transistor and to a source of the first transistor, wherein the third SIC comprises a plurality of legs in parallel with each other and coupled to the gate of the first transistor and the source of the first transistor, wherein each leg of the third SIC comprises a respective impedance element and a respective switch coupled to the respective impedance element; and   an inductor coupled between ground and the source of the first transistor.   
     
     
         15 . A method of operating the front-end circuit of  claim 1 , the method comprising:
 controlling the impedance value of the first SIC;   providing an LNA output signal to the LNA output based on an input signal received at the LNA input, wherein the input signal received at the LNA input is based on the input signal received at the input port; and   providing the output signal at the output port, wherein the output signal is based on the LNA output signal, the impedance value of the first SIC, and an impedance value of the output impedance matching network.   
     
     
         16 . A method of operating a front-end circuit, the method comprising:
 controlling an impedance value of a first switched impedance circuit (SIC) of the front-end circuit, wherein the first SIC is coupled in parallel with an output impedance matching network of the front-end circuit and coupled to a low noise amplifier (LNA) output of an LNA of the front-end circuit and to an output port of the front-end circuit, wherein the impedance value is based on a plurality of selectable impedances, and wherein the output impedance matching network is coupled between the LNA output and the output port;   providing an LNA output signal to the LNA output based on an input signal received at an input port of the front-end circuit, wherein the input signal has a frequency within one of at least two frequency ranges; and   providing an output signal at the output port, wherein the output signal is an amplified version of the received input signal and is based on the LNA output signal, the impedance value of the first SIC, and an impedance value of the output impedance matching network.   
     
     
         17 . The method of  claim 16 , wherein the first SIC comprises:
 a first terminal coupled to the LNA output;   a second terminal coupled to the output port; and   a plurality of legs in parallel with each other and coupled between the first terminal and to the second terminal, wherein each of the plurality of legs comprises a respective impedance element and a respective switch in series with the respective impedance element, wherein each leg of the first SIC has a respective first impedance value when the switch is closed and a respective second impedance value when the switch is open, and wherein the controlling the impedance value of the first SIC comprises selectively coupling each of the respective impedance elements between the LNA output and the output port.   
     
     
         18 . The method of  claim 17 , wherein:
 the plurality of legs comprises:
 a first leg comprising a first capacitor as its impedance element and a first switch in series with the first capacitor; 
 a second leg comprising a second capacitor as its impedance element and a second switch in series with the second capacitor; and 
 a third leg comprising a third capacitor as its impedance element and a third switch in series with the third capacitor; and 
   the controlling the impedance value of the first SIC comprises selectively coupling each of the first capacitor, the second capacitor, and the third capacitor between the LNA output and the output port.   
     
     
         19 . The method of  claim 16 , further comprising controlling an impedance value of a second SIC of the front-end circuit, wherein the second SIC is coupled to the LNA output and ground, wherein the output signal at the output port is further based on the impedance value of the second SIC, and wherein the second SIC comprises:
 a first terminal coupled to the LNA output;   a second terminal coupled to ground; and   a plurality of legs in parallel with each other, wherein each leg is between the first terminal and the second terminal and comprises a respective impedance element and a respective switch coupled to the respective impedance element, wherein each leg of the second SIC has a respective first impedance value when the switch is closed and a respective second impedance value when the switch is open, and wherein the respective switch of each leg is opened or closed based at least in part on the frequency of the input signal to control the impedance value of the second SIC.   
     
     
         20 . The method of  claim 19 , wherein the plurality of legs comprises:
 a first leg comprising a first impedance element and a first switch in series with the first impedance element;   a second leg comprising a second impedance element and a second switch in series with the second impedance element; and   a third leg comprising a third impedance element and a third switch in series with the third impedance element, wherein the controlling the impedance value of the second SIC comprises selectively coupling each of the first impedance element, the second impedance element, and the third impedance element between the LNA output and ground.   
     
     
         21 . The method of  claim 20 , wherein the plurality of legs further comprises a fourth leg comprising a fourth impedance element and a fourth switch in series with the fourth impedance element, and wherein the controlling the impedance value of the second SIC further comprises selectively coupling the fourth impedance element between the LNA output and ground. 
     
     
         22 . The method of  claim 21 , wherein each of the first, second, third, and fourth impedance elements comprises a respective capacitor, and wherein the plurality of legs further comprises:
 a fifth leg comprising a first resistor as its impedance element and a fifth switch in series with the first resistor;   a sixth leg comprising a second resistor as its impedance element and a sixth switch in series with the second resistor;   a seventh leg comprising a third resistor as its impedance element and a seventh switch in series with the third resistor; and   an eighth leg comprising a fourth resistor as its impedance element and an eighth switch in series with the fourth resistor,   wherein:
 the controlling the impedance value of the second SIC further comprises selectively coupling each of the first resistor, the second resistor, the third resistor, and the fourth resistor between the LNA output and ground; and 
 a fifth impedance element of the front-end circuit is coupled to the plurality of legs and to the LNA output. 
   
     
     
         23 . The method of  claim 16 , further comprising:
 receiving, by a bias control module, one or more input signals from a central control processor;   generating, by the bias control module, a bias voltage based on the one or more input signals; and   providing, by the bias control module, the bias voltage to a transistor of the LNA, wherein a gain associated with the LNA is based at least in part on the bias voltage.   
     
     
         24 . A front-end circuit comprising:
 means for selectively coupling each of a first plurality of impedance elements between a low noise amplifier (LNA) output of an LNA of the front-end circuit and an output port of the front-end circuit to select an impedance value associated with the first plurality of impedance elements from a plurality of selectable impedance values associated with the first plurality of impedance elements, wherein each of the first plurality of impedance elements is coupled to an output impedance matching network of the front-end circuit;   means for providing an LNA output signal to the LNA output based on an input signal received at an input port of the front-end circuit, wherein the input signal has a frequency within one of at least two frequency ranges; and   means for providing an output signal at the output port, wherein the output signal is an amplified version of the received input signal and is based on the LNA output signal, the selected impedance value associated with the first plurality of impedance elements, and an impedance value of the output impedance matching network.   
     
     
         25 . The front-end circuit of  claim 24 , wherein the first plurality of impedance elements comprises a first capacitor, a second capacitor, and a third capacitor, and wherein the means for selectively coupling comprises:
 means for selectively coupling the first capacitor between the LNA output and the output port;   means for selectively coupling the second capacitor between the LNA output and the output port; and   means for selectively coupling the third capacitor between the LNA output and the output port.   
     
     
         26 . The front-end circuit of  claim 24 , further comprising means for selectively coupling each of a second plurality of impedance elements between the LNA output and ground to select an impedance value associated with the second plurality of impedance elements from a plurality of selectable impedance values associated with the second plurality of impedance elements, wherein the means for selectively coupling each of the second plurality of impedance elements comprises:
 means for selectively coupling a first impedance element of the second plurality of impedance elements between the LNA output and ground;   means for selectively coupling a second impedance element of the second plurality of impedance elements between the LNA output and ground; and   means for selectively coupling a third impedance element of the second plurality of impedance elements between the LNA output and ground,   wherein the output signal is further based on the selected impedance value associated with the second plurality of impedance elements.   
     
     
         27 . The front-end circuit of  claim 26 , wherein the means for selectively coupling each of the second plurality of impedance elements further comprises means for selectively coupling a fourth impedance element of the second plurality of impedance elements between the LNA output and ground. 
     
     
         28 . The front-end circuit of  claim 27 , further comprising an impedance element coupled to the second plurality of impedance elements and to the LNA output, wherein:
 each of the first, second, third, and fourth impedance elements comprises a respective capacitor; and   the means for selectively coupling each of the second plurality of impedance elements further comprises:
 means for selectively coupling a first resistor of the second plurality of impedance elements between the LNA output and ground; 
 means for selectively coupling a second resistor of the second plurality of impedance elements between the LNA output and ground; 
 means for selectively coupling a third resistor of the second plurality of impedance elements between the LNA output and ground; and 
 means for selectively coupling a fourth resistor of the second plurality of impedance elements between the LNA output and ground. 
   
     
     
         29 . The front-end circuit of  claim 24 , further comprising:
 means for receiving one or more input signals from a central control processor;   means for generating a bias voltage based on the one or more input signals; and   means for providing the bias voltage to a transistor of the LNA, wherein a gain associated with the LNA is based at least in part on the bias voltage.